A cost effective PoP structure with high I/O density

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000768-000785
Author(s):  
Hongjie Wang ◽  
Weidong Huang ◽  
Fei Geng ◽  
Yuan Lu ◽  
Bo Zhang ◽  
...  
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Solder Bump ◽  
Cost Effective ◽  
Wire Bonding ◽  
Manufacturing Cost ◽  
Good Reliability ◽  
Solder Bumps ◽  
Package Size ◽  
Interconnection Structure

Package-on-package (PoP) structure is widely used in smart phones and tablets in which memory package is directly attached to the top of the application processor. As the market demands more speed and bandwidth, memory devices need more than 1000 I/Os to support future requirements. However← since the package size also becomes smaller and smaller, finer I/O pitch is absolutely required. Although using some new technology can achieve finer I/O pitch, it increases the manufacturing cost. Using traditional mature technology can reduce manufacturing cost, but has limitation in finer I/O pitch. So, it demands a reasonable balance between design, process and cost to develop an applicable PoP structure. In this paper we proposed a novel and cost effective PoP interconnection structure and a multi-layer PoP model. The PoP interconnection was formed by the solder ball on the top package connected to the solder bumps on the bottom package. The solder bump was made of a smaller solder ball attached on a Cu stud bump on the top of bottom substrate. The Cu stud bump was made through wire bonding machines and was coined so that the small solder ball can be attached to it. Using film assist molding technology, a half of the solder ball is exposed outside of molding compound, which can be connected with the solder ball of the top package through reflow process. This PoP interconnection structure was named solder bump through molding (BTM). A three layer PoP vehicle package was designed in our experiments. The top package was a wire bonding BGA, the middle and bottom packages were both flip chip BGA with BTM interconnection structure. The package size of these three packages was 10×10mm2 and ball pitch was 0.4mm. The assembly process of top package was as normal as other wire bonding BGA. The assembly processes of middle and bottom packages were as follows: The Cu stud bumps were first bonded to the top surface of the substrate using wire bonding machines. Small solder balls were attached to the top of Cu stud bumps using stencil tool and then reflowed. After solder bumps were made, all chips were flip bonded to the substrates. Then, using film assist molding and MUF technology, the chips were encapsulated and Cu stud bumps were half exposed. After all the packages were ready, the package stacking and reflow was performed one by one from top to the bottom and the overall three layer PoP was formed. C-scan test and cross section analysis showed that the encapsulation had no voids in most samples. Electrical test results showed the interconnection was good. Reliability study will be also discussed in this paper, which is still in research now. In BTM structure, both Cu stud and solder ball attach can be easily realized. The ball pitch can be 0.4mm or smaller and the process is also applicable for more layer PoP. Thus, BTM PoP structure provides a good solution considering the balance among cost, performance and manufacturing for 3D package. Acknowledgments The authors acknowledge the support of National Science and Technology Major Project (Project number：2013ZX02501003).

Non-Chemical Solder Bump Removal Technique for Repackaging Flip Chip ICs

2012 ◽  
Author(s):  
Mauri Sutton ◽  
George Geoghegan ◽  
Kenneth Schopen ◽  
Kathleen Kingma ◽  
Steve Castro ◽  
...  
Keyword(s):  
Success Rate ◽  
Flip Chip ◽  
Solder Bump ◽  
Wire Bonding ◽  
Solder Bumps ◽  
Bonding Area ◽  
Probe Card ◽  
Bond Pads ◽  
Removal Technique ◽  
Predictable Condition

Abstract In this paper we will discuss an empirically discovered technique to remove residual solder bumps or remnants using reflow and wicking to a gold plated surface rather than mechanical or chemical means. Extraction of flip chip ICs, for the purpose of repackaging, can leave bond pads in inconsistent and undesirable conditions such as 1) retaining remnants of the solder bumps or 2) damaged or eliminated pad metal caused by acid or mechanical means used to separate the IC from the board. These conditions hinder subsequent wire bonding and probe card use. Though other techniques have been found to be suitable at times, the technique described in this paper consistently leaves the bonding area in an acceptable, more predictable condition, as the bulk of the solder bump material is removed. This lends to a higher wire bonding success rate.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

Wafer Level Solder Bumping and Flip Chip Assembly with Solder Balls Down to 30μm

2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter
Keyword(s):  
Solder Ball ◽  
Flip Chip ◽  
Temperature Cycling ◽  
Solder Paste ◽  
Wafer Level ◽  
Solder Alloys ◽  
Flip Chips ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Cost Efficient

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.

Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter

2011 ◽  
Vol 2011 (1) ◽  
pp. 000985-000996 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Jörg Goßler ◽  
Jörg Franke
Keyword(s):  
Thermal Diffusion ◽  
Flip Chip ◽  
Solder Bump ◽  
Temperature Cycling ◽  
Sphere Diameter ◽  
Accelerated Life Tests ◽  
Flip Chips ◽  
Accelerated Life ◽  
Solder Bumps ◽  
Life Tests

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability. Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing. A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.

Application of Synchrotron Radiation X-Ray Micro-Tomography to Nondestructive Evaluation of Thermal Fatigue Damage in Flip Chip Interconnects

2007 ◽  
Author(s):  
Hiroyuki Tsuritani ◽  
Toshihiko Sayama ◽  
Yoshiyuki Okamoto ◽  
Takeshi Takayanagi ◽  
Kentaro Uesugi ◽  
...  
Keyword(s):  
Synchrotron Radiation ◽  
Fatigue Damage ◽  
Thermal Fatigue ◽  
Thermal Cycle ◽  
Flip Chip ◽  
Solder Bump ◽  
Fatigue Cracks ◽  
Phase Growth ◽  
X Ray ◽  
Solder Bumps

A synchrotron radiation X-ray micro-tomography system called SP-μCT with a spatial resolution of about 1μm has been developed in SPring-8, the largest synchrotron radiation facility in Japan. In this work, SP-μCT was applied to the nondestructive evaluation of microstructure evolution; that is phase growth, and micro-crack propagation appearing as thermal fatigue damage in solder micro-bumps of flip chip interconnects. The observed specimens have a flip chip structure joined by Sn-37wt%Pb eutectic solder bumps 100μm in diameter. A thermal cycle test was carried out, and the specimens were picked up at any number of cycles. The solder bumps were observed by using SP-μCT at the beamlines BL47XU and BL20XU in SPring-8. An X-ray energy of 29.0 keV was selected to obtain absorption images with a high contrast between the Sn-rich and the Pb-rich phases. Additionally, a refraction-contrast imaging technique was applied to visualize fatigue cracks in the solder bumps. The obtained CT (Computed Tomography) images clearly show the process of phase growth and crack propagation due to the thermal cyclic loading of the same solder bump; such information has not been obtained at all by industrially-used X-ray CT systems. In the initial state, the Pb-rich phase was dispersed with characteristic shape, which appears in reflow soldering process. Remarkable phase growth was also observed clearly as the thermal cycle test proceeded. When the loading reached 300 cycles, fatigue cracks appeared in the corners of the interfaces between the solder bump and the Cu pad. The CT images enabled us to evaluate the lifetime of the bumps to the initiation of fatigue cracks by estimating the increase in a phase growth parameter, which corresponds to the accumulation of fatigue damage in the solder joints. The results showed that the estimated lifetime strongly agreed with the average value, which was determined by SEM (Scanning Electron Microscope) destructive observations. As the thermal cycle proceeded, the cracks propagated gradually to the inner region of the solder bump. From the CT images, the average propagation rate was calculated, and the mean of the total fatigue lifetime was estimated to be less than 1800 cycles. These results show the possibility that nondestructive testing by a synchrotron radiation X-ray micro CT system is useful for evaluating the thermal fatigue lifetime in micro-joints.

Solder Joining Technology

1989 ◽  
Vol 154 ◽  
Author(s):  
Nick Koopman
Keyword(s):  
Flip Chip ◽  
Materials Design ◽  
Wire Bonding ◽  
Future Trends ◽  
Joining Technology ◽  
Solder Bumps ◽  
Design Factors

An in-depth review of controlled collapse chip connections (c-4), or otherwise known as Flip Chip Solder Joining Technology, is present. The C4 joint utilizes solder bumps deposited on wettable terminals on the chip and a matching footprint of the substrate. The upsidedown chip (flip chip) is aligned to the substrate and all joints are made simultaneously by reflowing the solder. An in depth review of this technology is presented. Materials, design factors, fabrication processes, tools, assembly, rework, and reliability are discussed. Future trends are indicated and comparisons make with wire bonding and Tab (tape automated bonding).

Sign in / Sign up

Export Citation Format

Share Document