Electrolytic Deposition of Fine Pitch Sn/Cu Solder Bumps for Flip Chip Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000729-000734
Author(s):  
Stephen Kenny ◽  
Kai Matejat ◽  
Sven Lamprecht ◽  
Olivier Mann
Keyword(s):  
Copper Alloy ◽  
Flip Chip ◽  
Solder Bump ◽  
Electroless Nickel ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Solder Bumps

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate alloy solder paste. The continuing trend towards increased miniaturization and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 150μm for these applications. This paper describes latest developments in the electrolytic deposition of solder to replace the stencil printing process; results from production of 90μm bump pitch solder arrays with tin/copper alloy are given. The solder bump is produced with a specially developed electrolytic tin process which fills a photo resist defined structure on the SRO. The photoresist dimensions determine the volume of solder produced and the subsequent bump height after reflow. Investigations on the bump reliability after reflow are shown including copper alloy concentration at 0.7% and x-ray investigation to confirm uniform metal deposition. The self centering mechanism found in the bump production process during reflow is presented and the capability to correct photoresist registration issues. The solder bumps are shown as deposited onto an electroless nickel/gold or electroless nickel/palladium/gold final finish which serves also as a barrier layer to copper diffusion into the solder bump. Discussion of further development work in the production of alloys of tin/copper together with silver are given with first test results.

Electrolytic Solder Deposit for Next Generation Flip Chip Solder Bumping

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 000671-000707
Author(s):  
Stephen Kenny ◽  
Sven Lamprecht ◽  
Kai Matejat ◽  
Bernd Roelfs
Keyword(s):  
Flip Chip ◽  
Practical Experience ◽  
Electrolytic Deposition ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Advantages And Disadvantages ◽  
Novel Approach ◽  
Solder Bumps ◽  
Chip Attachment

Electrolytic Solder Deposit for Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 μm. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper and also tin/silver are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy systems and also pure tin bumping are presented together with comparison of the advantages and disadvantages. The general advantages of replacement of stencil printing by electrolytic deposition of solder bumps are shown and in particular the improvement of bump reliability and the potential to significantly decrease costs by yield improvement.

A Study of the Aperture Filling Process in Solder Paste Stencil Printing

1999 ◽  
Author(s):  
Jianbiao Pan ◽  
Gregory L. Tonkay
Keyword(s):  
Flip Chip ◽  
Deposition Process ◽  
Area Ratio ◽  
Solder Paste ◽  
Stencil Printing ◽  
Printing Process ◽  
Surface Mount ◽  
Fine Pitch ◽  
Main Indicator ◽  
Advanced Packaging

Abstract Stencil printing has been the dominant method of solder deposition in surface mount assembly. With the development of advanced packaging technologies such as ball grid array (BGA) and flip chip on board (FCOB), stencil printing will continue to play an important role. However, the stencil printing process is not completely understood because 52–71 percent of fine and ultra-fine pitch surface mount assembly defects are printing process related (Clouthier, 1999). This paper proposes an analytical model of the solder paste deposition process during stencil printing. The model derives the relationship between the transfer ratio and the area ratio. The area ratio is recommended as a main indicator for determining the maximum stencil thickness. This model explains two experimental phenomena. One is that increasing stencil thickness does not necessarily lead to thicker deposits. The other is that perpendicular apertures print thicker than parallel apertures.

Analysis of the Micro-Mechanical Properties in Aged Lead-Free, Fine Pitch Flip Chip Joints

2003 ◽  
Author(s):  
Changqing Liu ◽  
Paul Conway ◽  
Dezhi Li ◽  
Michael Hendriksen
Keyword(s):  
Shear Strength ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Initial Period ◽  
Electroless Nickel ◽  
Circuit Board ◽  
Solder Paste ◽  
Soldering Process ◽  
Joint Reliability ◽  
Solder Bumps

This research seeks to characterize the micro-mechanical behavior of Sn-Ag-Cu solder bumps/joints generated by fine feature flip chip fabrication and assembly processes. The bumps used for characterization were produced by stencil deposition of solder paste onto an electroless Nickel UBM, followed by a bump-forming reflow soldering process and the final assembly joints were then achieved by a subsequent reflow of die onto a fine feature Printed Circuit Board (PCB). The bumps and joints were aged at either 80°C or 150°C for up to 1.5 months and then analyzed by means of micro-shear testing and nano-indentation techniques. The shear test of the aged bumps showed a slight increase in shear strength after an initial period of aging (∼ 50h) as compared to as-manufactured bumps, but a decrease after longer aging (e.g. 440 h). A brittle Ag3Sn phase formed as large lamellae in the solder and along the interface between the Cu on the PCB during the initial aging, and is attributed to the increase of shear strength, along with the refinement of the bump microstructure. However, as the time of aging extended, the solder bumps were softened due to grain growth and re-crystallization. It was found that the formation of brittle phases in the solder and along the interfaces caused localized stress concentration, which can significantly affect joint reliability. In addition, Nano-testing identified a lamellar Au-rich structure, formed in the solder and interface of the solder/PCB in the joints after the aging process. These are believed to be detrimental to joint reliability.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

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