On the Way from Fan-out Wafer to Fan-out Panel Level Packaging

2016 ◽  
Vol 2016 (S2) ◽  
pp. S1-S23 ◽  
Author(s):  
Karl-Friedrich Becker ◽  
Tanja Braun ◽  
S. Raatz ◽  
M. Minkus ◽  
V. Bader ◽  
...  
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Layer Structure ◽  
Form Factors ◽  
Circuit Board ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Bga Packages ◽  
Wire Bonds ◽  
Near Future

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Manufacturing is currently done on wafer level up to 12″/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18″×24″ or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

Wafer Level Packaging Cost Modeling

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002312-002325 ◽  
Author(s):  
Chet A. Palesko
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Cost Effective ◽  
Circuit Board ◽  
Wafer Level ◽  
Design Rules ◽  
Wafer Level Packaging ◽  
Cost Effective Approach ◽  
Significant Difference ◽  
Interconnect Design

Wafer level packaging is often the most cost effective approach to achieve miniaturization. However, if it is used for the wrong application, it can be very expensive. The significant difference in printed circuit board interconnect design rules and semiconductor interconnect design rules must be addressed in any type of packaging approach, and presents unique challenges for wafer level packaging. If miniaturization is not required, this translation of semiconductor design rules to PCB design rules is most easily accomplished in a traditional wire bond package. However, when the package size and the die size must be the same, the package IO count is limited. Fanout WLP is an option to overcome the WLP IO restriction, but still achieve cost effective miniaturization. We will present the results of activity based cost and yield modeling of traditional wafer level packaging, fanout wafer level packaging, and flip chip packaging across a range of die sizes, package sizes, and defect densities. These results will show the most cost effective technology to match a variety of applications and package parameters.

On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou
Keyword(s):  
Technological Change ◽  
Flip Chip ◽  
Emerging Technologies ◽  
Unit Area ◽  
Form Factors ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Wafer Level Packaging ◽  
Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

In-Situ Mechanical Sample Preparation of Selected Sites and Components on Large Modules and Boards

2016 ◽  
Author(s):  
Jim Colvin ◽  
Timothy Hazeldine ◽  
Heenal Patel
Keyword(s):  
Sample Preparation ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Tilt Table ◽  
Standard Requirement ◽  
Open Design ◽  
Bga Packages ◽  
Silicon Thickness ◽  
Board Level

Abstract The standard requirement for FA Engineers needing to remove components from a board, prior to decapsulation or sample preparation, is shown to be greatly reduced, by the methods discussed here. By using a mechanical selected area preparation system with an open-design it is possible to reach all required areas of a large printed circuit board (PCB) or module to prepare a single component ‘in situ’. This makes subsequent optical or electrical testing faster and often more convenient to accomplish. Electronic End-pointing and 3D curvature compensation methods can often be used in parallel with sample prep techniques to further improve the consistency and efficacy of the decapsulation and thinning uniformity and final remaining silicon thickness (RST). Board level prep eliminates the worry of rework removal of BGA packages and the subsequent risk of damage to the device. Since the entire board is mounted, the contamination is restricted to the die surface and can be kept from the underside ball connections unlike current liquid immersion methods of package thinning or delayering. Since the camera is in line with the abrasion interface, imaging is real time during the entire milling and thinning process. Recent advances in automated tilt-table design have meant that a specific component’s angular orientation can be optimized for sample preparation. Improved tilt table technology also allows for improved mounting capability for boards of many types and sizes. The paper describes methods for decapsulation, thinning and backside polishing of a part ‘in situ’ on the polishing machine and allows the system to operate as a probe station for monitoring electrical characteristics while thinning. Considerations for designing board-level workholders are described – for boards that that are populated with components on one or even both sides. Using the techniques described, the quality of sample preparation and control is on a par with the processing of single package-level devices.

scholarly journals Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

2021 ◽  
pp. 1-9
Author(s):  
Philipp Ritter
Keyword(s):  
Millimeter Wave ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Digital Signal ◽  
Cmos Technology ◽  
Radar System ◽  
Circuit Board ◽  
Processing Unit ◽  
Automotive Radar ◽  
On Chip

Abstract Next-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

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