scholarly journals DESIGN OF LOW VOLTAGE LOW POWER OPERATIONAL AMPLIFIER

2015 ◽  
pp. 257-261
Author(s):  
M.I.SUDHA RAYAPPA ◽  
V. SURENDRA BABU
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Operational Amplifier ◽  
Noise Level ◽  
Low Voltage ◽  
High Gain ◽  
Op Amp ◽  
Technology Improvement ◽  
Supply Voltages ◽  
Analog Systems

This Thesis presents a design of the Folded-cascade operational amplifier which leads to high gain as compared to a normal cascade circuit. In this project; specifications of analog systems into op amp level net-lists of library components is studied and simulated using XILINX. As the power-supply voltages because of the technology improvement and it are desired to reduce power supply to minimize power dissipation, many challenges are faced by the analog designer. One is to keep noise level as possible. The op-amp must be designed to with the ever decreasing power supply voltages. As the power supply voltages begin to approach 2Vt, new technique and new op-amp topology like folded cascade should be used.

Design of a Rail-to-Rail Operational Amplifier with Low Supply Voltage and Low Power Dissipation

2013 ◽  
Vol 380-384 ◽  
pp. 3275-3278
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Hai Huang ◽  
Chang Chun Dong
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
High Gain ◽  
Op Amp ◽  
Rail To Rail ◽  
Dc Gain ◽  
Low Power Dissipation ◽  
Static Power ◽  
Low Supply Voltage

An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage slew rate of 8.2V/μS,an input and output range of 0-3.3V,when operating at 3.3V power supply and a 20pF output load.

scholarly journals Design and PVT Analysis of Robust, High Swing Folded Cascode Operational Amplifier

2019 ◽  
Vol 9 (2) ◽  
pp. 114-118
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Op Amp ◽  
Multistage Amplifiers ◽  
Pvt Variations ◽  
Folded Cascode ◽  
Voltage Swing

The folded cascode operational amplifier (FCOA) designed in this paper is the single-pole operational amplifier (op amp). In this design, the conventional current mirror is replaced with wide swing current mirror to overcome the essential drawback of cascode configuration. In this paper, negative feedback is used to improve the small-signal gain and to ensure better stability than multistage amplifiers. This paper also aims at improving the output voltage swing, power dissipation and robustness of the op amp. The designed FCOA is proficient in achieving 67.44dB gain and 1.77V output swingat typical voltage for 180nm CMOS technology. The FCOA is highly stable with phase margin of 62.58º while dissipating 0.5mW power. This amplifier is further verified for variability analysis for Process, Voltage and Temperature (PVT) variations to check robustness. All together testing is done at 45 different PVT combinations and results are tabulated accordingly. At each corner temperature and voltage are varied for all together nine combinations to properly address the effect of PVT variations. The results shows that the op amp exhibits desired response at four corners (FF, TT, SS, and FS) of process, over -40º to 125º C temperature range. Also it is capable of operating at very low voltage up to 0.9V adequately showing reduction in power dissipation. Thus the designed op amp is low power, high swing and robust towards process, voltage and temperature variations.

A Robust SOI Gain-Boosted Operational Amplifier Targeting High Temperature Precision Applications up to 300°C

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000238-000242
Author(s):  
Alexander Schmidt ◽  
Abdel Moneim Marzouk ◽  
Holger Kappert ◽  
Rainer Kokozinski
Keyword(s):  
High Temperature ◽  
Circuit Design ◽  
Robust Design ◽  
Wide Temperature Range ◽  
Operational Amplifier ◽  
Operating Temperature ◽  
High Gain ◽  
Temperature Range ◽  
Op Amp ◽  
Operating Temperature Range

Data acquisition and signal processing at elevated temperatures are facing various problems due to a wide temperature range operation, affecting the accuracy of the circuits' references and elementary building blocks. As the most commonly used analog building block, the operational amplifier (op-amp) with its various limitations has to be enhanced for wide temperature range operation. Thereby major effort is put into maximizing signal gain and simultaneously reaching high gain-bandwidth also for high temperatures. Future robust design approaches have to consider a growing operating temperature range and increasing device parameter mismatch due to the downsizing of integrated circuits. Addressing one of the major problems in circuit design for the next decades, compensating these effects through new design approaches will have a lasting impact on circuit design. In this paper we present a high gain operational amplifier with a folded-cascode and gain-boosted input stage, fabricated in a 1.0 μm SOI CMOS process. The operational amplifier was designed for an operating temperature range of −40…300°C. Major effort was put into a robust design approach with reduced sensitivity to temperature variations, targeting high precision applications in a high temperature environment. With a supply voltage of 5 V, the maximum simulated current consumption of the op-amp is 210 μA which leads to overall maximum power consumption of 1.05 mW. The open loop DC gain of the amplifier is expected to reach a minimum of 108 dB and a unity-gain-frequency of 1.02 MHz at a temperature of 300°C. For all temperatures the phase margin varies from 55…70 degrees for a 3 pF load.

Design Low Voltage FGMOS Operational Amplifier for Power Applications

2012 ◽  
Vol 433-440 ◽  
pp. 4189-4193 ◽  
Author(s):  
M. B. K. Jamal ◽  
S. P. Chew ◽  
B. I. Khadijah ◽  
S. B. M. Noormiza
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Electronic Device ◽  
Supply Voltage ◽  
High Gain ◽  
Battery Life ◽  
Op Amp ◽  
Integration Density ◽  
Low Power Dissipation ◽  
High Bandwidth

Due to the rise in demand for portable electronic device, low power and low voltage circuit design is extremely important for the appliances like computers, laptops, mobile phones and etc. Low power dissipation results in longer battery life and better integration density. This can be achieved by designing a modified low voltage op amp. The design of low voltage op amp in this paper is the combination of several low voltage analog cells. The modified low power op amp in this paper is built based on low voltage basic op amp. In this paper, the design objective is to achieve certain criteria such as supply voltage as low as 1 V, high gain more than 40 dB, low power consumption and high bandwidth. The use of FGMOS would increase the operating range of op amp through programming the threshold voltage of the FGMOS. This project is simulated using Silvaco Gateway and Expert.

scholarly journals Design of very low-voltages and high-performance CMOS gate-driven operational amplifier

2020 ◽  
Vol 20 (2) ◽  
pp. 670
Author(s):  
Hayder Khaleel AL-Qaysi ◽  
Musaab Mohammed Jasim ◽  
Siraj Manhal Hameed
Keyword(s):  
Power Supply ◽  
Operational Amplifier ◽  
High Performance ◽  
Power Supplies ◽  
Slew Rate ◽  
Op Amp ◽  
Rejection Ratio ◽  
Power Supply Rejection Ratio ◽  
Performance Specifications ◽  
Simulation Results

This paper presents the description and analysis of the design and HSPICE-based simulation results of very low-voltages (LVs) power supplies and high-performance specifications CMOS gate-driven (GD) operational amplifier (Op-Amp) circuit. The very LVs CMOS GD Op-Amp circuit designed using 90nm CMOS technology parameters and the folded cascode (FC) technique employed in the differential input stage. The HSPICE simulation results demonstrate that the overall gain is 73.1dB, the unity gain bandwidth is 14.9MHz, the phase margin is , the total power dissipation is 0.91mW, the output voltage swing is from 0.95V to 1V, the common-mode rejection ratio is dB, the equivalent input-referred noise voltage is 50.94  at 1MHz, the positive slew rate is 11.37 , the negative slew rate is 11.39 , the settling time is 137 , the positive power-supply rejection ratio is 74.2dB, and the negative power-supply rejection ratio is 80.1dB. The comparisons of simulation results at 1V and 0.814V power supplies’ voltages of the very LVs CMOS GD Op-Amp circuit demonstrate that the circuit functions with perfect performance specifications, and it is suitable for many considerable applications intended for very LVs CMOS Op-Amp circuits.

Sign in / Sign up

Export Citation Format

Share Document