Design of a Rail-to-Rail Operational Amplifier with Low Supply Voltage and Low Power Dissipation

2013 ◽  
Vol 380-384 ◽  
pp. 3275-3278
Author(s):  
Zhan Peng Jiang ◽  
Rui Xu ◽  
Hai Huang ◽  
Chang Chun Dong
Keyword(s):  
Power Dissipation ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
High Gain ◽  
Op Amp ◽  
Rail To Rail ◽  
Dc Gain ◽  
Low Power Dissipation ◽  
Static Power ◽  
Low Supply Voltage

An rail-to-rail operational amplifier is presented in this paper, which is designed by with two op amp, the first level of the structure is the complementary differential structure which will providing input for the operational amplifier, the second level is designed with the structure of folding cascode to get a high gain. The operational amplifier is designed with the TSMC 0.35u m3.3VCMOS mixed analog-digital technology library. The simulated results show that the operational amplifier has a DC gain of 110dB,a GBW of 9.5MHz,a static power dissipation of 0.95mW,a phase margin of 73°,a voltage slew rate of 8.2V/μS,an input and output range of 0-3.3V,when operating at 3.3V power supply and a 20pF output load.

A Direct Bulk Coupling PMOS Colpitts QVCO Using Capacitive-Feedback Structure

2019 ◽  
Vol 28 (08) ◽  
pp. 1950125
Author(s):  
Jianqun Ding ◽  
Lijun Huang ◽  
Xianwu Mi ◽  
Dajiang He ◽  
Shenghai Chen ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Figure Of Merit ◽  
Supply Voltage ◽  
Voltage Controlled Oscillator ◽  
Chip Area ◽  
Low Power Dissipation ◽  
Feedback Structure ◽  
Voltage Swing ◽  
Low Supply Voltage ◽  
Capacitive Feedback

In this paper, a full PMOS Colpitts quadrature voltage-controlled oscillator (QVCO) topology, suitable for low supply voltage and low power dissipation, is presented. For an enhanced voltage swing under a low supply voltage, the capacitive-feedback technique is employed. Quadrature coupling is achieved by employing direct bulk coupling technique, leading to reduction in both power and chip area. The proposed QVCO covers a 5% tuning range between 2.325 GHz and 2.435 GHz, and the phase noise is [Formula: see text]128.2 dBc/Hz at 1-MHz offset from the 2.34-GHz carrier while consuming only 0.535 mW from 0.55-V supply voltage, yielding a figure-of-merit (FoM) of 198 dBc/Hz.

Design Low Voltage FGMOS Operational Amplifier for Power Applications

2012 ◽  
Vol 433-440 ◽  
pp. 4189-4193 ◽  
Author(s):  
M. B. K. Jamal ◽  
S. P. Chew ◽  
B. I. Khadijah ◽  
S. B. M. Noormiza
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Electronic Device ◽  
Supply Voltage ◽  
High Gain ◽  
Battery Life ◽  
Op Amp ◽  
Integration Density ◽  
Low Power Dissipation ◽  
High Bandwidth

Due to the rise in demand for portable electronic device, low power and low voltage circuit design is extremely important for the appliances like computers, laptops, mobile phones and etc. Low power dissipation results in longer battery life and better integration density. This can be achieved by designing a modified low voltage op amp. The design of low voltage op amp in this paper is the combination of several low voltage analog cells. The modified low power op amp in this paper is built based on low voltage basic op amp. In this paper, the design objective is to achieve certain criteria such as supply voltage as low as 1 V, high gain more than 40 dB, low power consumption and high bandwidth. The use of FGMOS would increase the operating range of op amp through programming the threshold voltage of the FGMOS. This project is simulated using Silvaco Gateway and Expert.

scholarly journals DESIGN OF LOW VOLTAGE LOW POWER OPERATIONAL AMPLIFIER

2015 ◽  
pp. 257-261
Author(s):  
M.I.SUDHA RAYAPPA ◽  
V. SURENDRA BABU
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Operational Amplifier ◽  
Noise Level ◽  
Low Voltage ◽  
High Gain ◽  
Op Amp ◽  
Technology Improvement ◽  
Supply Voltages ◽  
Analog Systems

This Thesis presents a design of the Folded-cascade operational amplifier which leads to high gain as compared to a normal cascade circuit. In this project; specifications of analog systems into op amp level net-lists of library components is studied and simulated using XILINX. As the power-supply voltages because of the technology improvement and it are desired to reduce power supply to minimize power dissipation, many challenges are faced by the analog designer. One is to keep noise level as possible. The op-amp must be designed to with the ever decreasing power supply voltages. As the power supply voltages begin to approach 2Vt, new technique and new op-amp topology like folded cascade should be used.

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

2020 ◽  
Vol 37 (4) ◽  
pp. 205-213
Author(s):  
Norhamizah Idros ◽  
Zulfiqar Ali Abdul Aziz ◽  
Jagadheswaran Rajendran
Keyword(s):  
Operational Amplifier ◽  
Open Loop ◽  
Cmos Process ◽  
Silicon Area ◽  
Content Type ◽  
Op Amp ◽  
Dc Gain ◽  
Input Range ◽  
Folded Cascode ◽  
The Impact

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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