scholarly journals A TRANSISTOR LEVEL ANALYSIS FOR A 8-BIT VEDIC MULTIPLIER

2012 ◽  
pp. 78-83
Author(s):  
ARUN K PATRO ◽  
KUNAL N DEKATE
Keyword(s):  
Power Consumption ◽  
Digital Signal ◽  
Cmos Technology ◽  
Total Power ◽  
Vedic Multiplier ◽  
Total Power Consumption ◽  
Improved Performance ◽  
Almost All ◽  
Signal Processors ◽  
Level Analysis

Power and area efficient multiplier using CMOS logic circuits for applications in various digital signal processors is designed. This multiplier is implemented using Vedic multiplication algorithms mainly the "Urdhvatiryakbhyam sutra" , which is the most generalized one Vedic multiplication algorithm [1] . A multiplier is a very important element in almost all the processors and contributes substantially to the total power consumption of the system. The novel point is the efficient use of Vedic algorithm (sutras) that reduces the number of computational steps considerably compared with any conventional method . The schematic for this multiplier is designed using TANNER TOOL. The design is then verified in T-SPICE using 0.18 um CMOS technology library file. The analysis is made for various voltages across a range of 2.5V to 5V, to validate the design. A CMOS digital multiplier, with low power consumption and high linearity is proposed. The results prove that the proposed multiplier consumes 80% less power compared to the gate level analysis done earlier. The core area of the proposed multiplier is 737 um2 . Paper presents a systematic design methodology for this improved performance digital multiplier based on Vedic mathematics.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

scholarly journals Design of Area Efficient, Low-Power and Reliable Transmission Gate-based 10T SRAM Cell for Biomedical Application

2021 ◽  
Author(s):  
Aswini Valluri ◽  
◽  
Sarada Musala ◽  
Muralidharan Jayabalan ◽  
◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Biomedical Application ◽  
Cmos Technology ◽  
Total Power ◽  
Silicon Area ◽  
Transmission Gate ◽  
Read Operation ◽  
Sram Cell ◽  
Total Power Consumption

There is an immense necessity of several kilo bytes of embedded memory for Biomedical systems which typically operate in the sub-threshold domain with perfect efficiency. SRAMs (Static Random Access Memory) dominates the total power consumption and the overall silicon area, as 70% of the die has been occupied by them. This brief proposes the design of a Transmission gate-based SRAM cell for Bio medical application eliminating the use of peripheral circuitry during the read operation. It commences the read operation directly with the help of Transmission gates with which the data stored in the storage nodes can be read, instead of using the precharge and sense amplifier circuits which suits better for the implantable devices. This topology offers smaller area, reduced delay, low power consumption as well as improved data stabilization in the read operation. The cell is implemented in 45nm CMOS technology operated at 0.45V.

Design of a 10-Bit High Performance Current-Steering DAC with a Novel Nested Decoder Based on Domino Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550086 ◽  
Author(s):  
Masoud Nazari ◽  
Leila Sharifi ◽  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Range ◽  
Logic Gates ◽  
Cmos Technology ◽  
Total Power ◽  
Current Steering ◽  
Domino Logic ◽  
Chip Area ◽  
Total Power Consumption

In this paper, a 10-bit 8-2 segmented current-steering digital-to-analog converter (DAC) is presented which uses a novel nested binary to thermometer (BT) decoder based on domino logic gates. High accuracy and high performances are achieved with this structure. The proposed decoder has a pipelining scheme and it is designed symmetrically in three stages with repeatable logic gates. Thus, power consumption, chip area and the number of control signals are reduced. The proposed DAC is simulated in 0.18-μm CMOS technology and the spurious-free dynamic range (SFDR) is 65.3 dB over a 500 MHz output bandwidth at 1 GS/s. Total power consumption of the designed DAC is only 23.4 mW while the digital and analog supply voltages are 1.2 and 1.8 V, respectively. The active area of the proposed DAC is equal to 0.3 mm2.

scholarly journals LOW POWER SI-BASED POWER AMPLIFIER FOR HEALTHCARE APPLICATION

2016 ◽  
Vol 8 (9) ◽  
pp. 307 ◽  
Author(s):  
Wei Cai ◽  
Cheng Li ◽  
Heng Gu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Amplifier ◽  
Process Variations ◽  
Cmos Technology ◽  
Total Power ◽  
Power Added Efficiency ◽  
Trade Offs ◽  
Total Power Consumption ◽  
Class B

<p><strong>Objective: </strong>The objective of this research was to design a 2.4 GHz class B Power Amplifier (PA), with 0.18um Semiconductor Manufacturing International Corporation (SMIC) CMOS technology by using Cadence software, for health care applications. The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.</p><p><strong>Methods: </strong>This paper introduces the design of a 2.4GHz class B power amplifier designed as dual gate topology. This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.</p><p><strong>Results:</strong> Besides, accurate device modeling, is needed, due to the leakage and process variations.</p><p><strong>Conclusion</strong>:<strong> </strong>The performance of the power amplifier meets the specification requirements of the desired.</p>

scholarly journals Dual Band Switchable Voltage Controlled Oscillator in 65-nm CMOS Technology

2020 ◽  
pp. 31-34
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Cmos Technology ◽  
Dual Band ◽  
Total Power ◽  
Voltage Controlled Oscillator ◽  
Dual Frequency ◽  
Chip Area ◽  
Total Power Consumption ◽  
Oscillation Frequencies

A switchable differential voltage-controlled oscillator (VCO) has been fabricated in 65nm CMOS. It is a dual frequency VCO whose oscillation frequencies can be changed from 40GHz (VCO1) to 80GHz (VCO2). The tuning range for VCO1 is 1GHz and for VCO2 is 4GHz. The inductor switching is attained with the help of transistor as a switch and inductors are fabricated in a stacked manner for saving die area. The output power of VCO1 is 1 dBm and for VCO2 is 0dBm with a total power consumption of 42mW. The phase noises were -94.62 dBc/Hz and -81.43 dBc/Hz at 1MHz offset for VCO1 and VCO2 respectively. The chip area is 500 x 560 um2 including probing pads.

scholarly journals DESIGN OF A 500MHZ, 4-BIT LOW POWER ADC FOR UWB APPLICATION

2014 ◽  
pp. 81-86
Author(s):  
SANTOSH KUMAR PATNAIK ◽  
DR. SWAPNA BANERJEE
Keyword(s):  
Power Consumption ◽  
Input Signal ◽  
Power Supply ◽  
Cmos Technology ◽  
Sampling Frequency ◽  
Total Power ◽  
Digital Converter ◽  
Analog To Digital ◽  
Total Power Consumption ◽  
Single Power

This paper presents a new topology of an Analog-to-Digital Converter (ADC), named as Switched Reference ADC (SR-ADC) where the reference voltages are applied through switches. The switched reference voltage concept works with few mutually exclusive switches which are appropriately selecting the reference voltages for comparison with the input signal. This SR-ADC has been implemented using 0.18μm single poly and six metal CMOS technology. The spectra simulation result of this SR-ADC shows an ENOB of ≈3.53 for a 1V peak-to-peak input signal having a frequency of 100MHz while operating at a sampling frequency of 500MHz. The total power consumption is 21.39mW for a single power supply of 1.8V having a core area of ≈253μm*221μm.

scholarly journals Efficient Operation Method of Aquifer Thermal Energy Storage System Using Demand Response

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3129
Author(s):  
Jewon Oh ◽  
Daisuke Sumiyoshi ◽  
Masatoshi Nishioka ◽  
Hyunbae Kim
Keyword(s):  
Energy Storage ◽  
Power Consumption ◽  
Thermal Energy ◽  
Demand Response ◽  
Thermal Energy Storage ◽  
Heat Storage ◽  
Storage System ◽  
Total Power ◽  
Operation Method ◽  
Total Power Consumption

The mass introduction of renewable energy is essential to reduce carbon dioxide emissions. We examined an operation method that combines the surplus energy of photovoltaic power generation using demand response (DR), which recognizes the balance between power supply and demand, with an aquifer heat storage system. In the case that predicts the occurrence of DR and performs DR storage and heat dissipation operation, the result was an operation that can suppress daytime power consumption without increasing total power consumption. Case 1-2, which performs nighttime heat storage operation for about 6 h, has become an operation that suppresses daytime power consumption by more than 60%. Furthermore, the increase in total power consumption was suppressed by combining DR heat storage operation. The long night heat storage operation did not use up the heat storage amount. Therefore, it is recommended to the heat storage operation at night as much as possible before DR occurs. In the target area of this study, the underground temperature was 19.1 °C, the room temperature during cooling was about 25 °C and groundwater could be used as the heat source. The aquifer thermal energy storage (ATES) system in this study uses three wells, and consists of a well that pumps groundwater, a heat storage well that stores heat and a well that used heat and then returns it. Care must be taken using such an operation method depending on the layer configuration.

scholarly journals A Novel Differential Log-Companding Amplifier for Biosignal Sensing

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Zigang Dong ◽  
Xiaolin Zhou ◽  
Yuanting Zhang
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Nonlinear Function ◽  
New Method ◽  
Total Power ◽  
Maximum Output ◽  
Output Current ◽  
Current Range ◽  
Symmetrical Configuration ◽  
Total Power Consumption

We proposed a new method for designing the CMOS differential log-companding amplifier which achieves significant improvements in linearity, common-mode rejection ratio (CMRR), and output range. With the new nonlinear function used in the log-companding technology, this proposed amplifier has a very small total harmonic distortion (THD) and simultaneously a wide output current range. Furthermore, a differential structure with conventionally symmetrical configuration has been adopted in this novel method in order to obtain a high CMRR. Because all transistors in this amplifier operate in the weak inversion, the supply voltage and the total power consumption are significantly reduced. The novel log-companding amplifier was designed using a 0.18 μm CMOS technology. Improvements in THD, output current range, noise, and CMRR are verified using simulation data. The proposed amplifier operates from a 0.8 V supply voltage, shows a 6.3 μA maximum output current range, and has a 6 μW power consumption. The THD is less than 0.03%, the CMRR of this circuit is 74 dB, and the input referred current noise density is166.1 fA/Hz. This new method is suitable for biomedical applications such as electrocardiogram (ECG) signal acquisition.

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