Pentacene Active Channel Layers Prepared by Spin-Coating and Vacuum Evaporation Using Soluble Precursors for OFET Applications

Pentacene OFETs of bottom-gate/bottom-contact were fabricated with three types of pentacene organic semiconductors and cross linked Poly(4-vinylphenol) or polycarbonate as gate dielectric layer. Two different processes were used to prepare the pentacene active channel layers: (1) spin-coating on dielectric layer using two different soluble pentacene precursors of SAP and DMP; (2) vacuum evaporation on PC insulator. X-ray diffraction studies revealed coexistence of thin film and bulk phase of pentacene from SAP and thin film phase of pentacene from DMP precursors. The field effect mobility of 0.031 cm2/Vs and threshold voltage of −12.5 V was obtained from OFETs fabricated from SAP precursor, however, the pentacene OFETs from DMP under same preparation yielded high mobility of 0.09 cm2/Vs and threshold value decreased to −5 V. It reflects that the mixed phase films had carrier mobilities inferior to films consisting solely of single phase. For comparison, we have also fabricated pentacene OFETs by vacuum evaporation on polycarbonate as the gate dielectric and obtained charge carrier mobilities as large as 0.62 cm2/Vs and threshold voltage of −8.5 V. We demonstrated that the spin-coated pentacene using soluble pentacene precursors could be alternative process technology for low cost, large area and low temperature fabrication of OFETs.

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Synthesis of ZnO Nanoparticles to Fabricate a Mask-Free Thin-Film Transistor by Inkjet Printing

Journal of Nanotechnology ◽

10.1155/2012/710908 ◽

2012 ◽

Vol 2012 ◽

pp. 1-8 ◽

Cited By ~ 7

Author(s):

Chao-Te Liu ◽

Wen-Hsi Lee ◽

Tsu-Lang Shih

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Zno Nanoparticles ◽

Inkjet Printing ◽

Carrier Mobility ◽

Gate Dielectric ◽

Low Cost ◽

Thin Film Transistor ◽

Flexible Displays ◽

Active Channel

We report a low-cost, mask-free, reduced material wastage, deposited technology using transparent, directly printable, air-stable semiconductor slurries and dielectric solutions. We have demonstrate an emerging process for fabricating printable transistors with ZnO nanoparticles as the active channel and poly(4-vinylphenol) (PVP) matrix as the gate dielectric, respectively, and the inkjet-printed ZnO TFTs have shown to exhibit the carrier mobility of 0.69 cm2/Vs and the threshold voltage of 25.5 V. We suggest that the printable materials and the printing technology enable the use of all-printed low-cost flexible displays and other transparent electronic applications.

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Effect of Novel Nanocomposite Materials for Enhancing Performance of Thin Film Transistor TFT Model

International Journal of Advances in Applied Sciences ◽

10.11591/ijaas.v5.i1.pp1-12 ◽

2016 ◽

Vol 5 (1) ◽

pp. 1

Author(s):

Youssef Ahmed Mobarak ◽

Moamen Atef

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Gate Dielectric ◽

Low Cost ◽

Thin Film Transistor ◽

Analytical Models ◽

Short Channel ◽

High K ◽

Wide Range ◽

Low K

The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La2O3Kox=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO2Ksp=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.

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Fabrication of a-Si:H Tfts at 120°C on Flexible Polyimide Substrates

MRS Proceedings ◽

10.1557/proc-558-375 ◽

1999 ◽

Vol 558 ◽

Cited By ~ 7

Author(s):

Andrei Sazonov ◽

Arokia Nathan ◽

R.V.R. Murthy ◽

S.G. Chamberlain

Keyword(s):

Thin Film ◽

Gate Dielectric ◽

Low Cost ◽

Thin Film Transistor ◽

Performance Comparison ◽

Hydrogen Gas ◽

Large Area ◽

Plastic Substrates ◽

Glass Substrates ◽

Contact Metallization

ABSTRACTThe fabrication of large-area thin-film transistor (TFT) arrays on thin flexible plastic substrates requires deposition of thin film layers at relatively low temperatures since the upper working temperature of low-cost plastic films should not exceed ∼200°C. In this paper, we report a fabrication process of a-Si:H TFTs at 120°C on flexible polyimide substrates for large-area imaging applications.Kapton HN (DuPont) films 50 and 125 μm thick and 3 inches in diameter, were used as substrates. Both sides of the polyimide substrate were first covered with 0.5 μm thick a-SiNx. The TFT structure includes: 120 nm thick room-temperature sputtered Al gate, 250 nm thick PECVD deposited a-SiNx for the gate dielectric, 50 nm thick a-Si:H deposited by PECVD from silane-hydrogen gas mixture, 50 nm thick n+ a-Si:H source- and drain contacts, and roomtemperature sputtered Al top contact metallization. We used dry etching for all layers except for the gate and top metal, which were patterned using wet etchants. For purpose of TFT performance comparison, Coming 7059 glass substrates were used.The performance of the fabricated TFT and its improvement with use of optimized a-Si:H and a-SiNx quality will be presented along with a discussion of the intrinsic mechanical stress in the thin film layers will also be discussed.

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Bias-Induced Threshold Voltage Shifts in Organic Thin-Film Transistors by Soluble Fullerene Layers on Gate Dielectric

Japanese Journal of Applied Physics ◽

10.1143/jjap.50.01bc04 ◽

2011 ◽

Vol 50 ◽

pp. 01BC04 ◽

Cited By ~ 4

Author(s):

Khairul Anuar Mohamad ◽

Katsuhiro Uesugi ◽

Hisashi Fukuda

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Organic Thin Film Transistors ◽

Organic Thin Film

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Analyzing and Increasing Yield of ZnO Thin-Film Transistors for Large-area Sensing Systems by Preventing Process-Induced Gate Dielectric Breakdown

2019 Device Research Conference (DRC) ◽

10.1109/drc46940.2019.9046406 ◽

2019 ◽

Author(s):

Zhiwu Zheng ◽

Levent E. Aygun ◽

Yoni Mehlman ◽

Sigurd Wagner ◽

Naveen Verma ◽

...

Keyword(s):

Thin Film ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Dielectric Breakdown ◽

Zno Thin Film ◽

Large Area ◽

Sensing Systems

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SuPR-NaP Technique for Printing Ultrafine Silver Electrodes and its Use for Low-Voltage Operation of Organic Thin-Film Transistors

MRS Advances ◽

10.1557/adv.2018.423 ◽

2018 ◽

Vol 3 (49) ◽

pp. 2931-2936

Author(s):

G. Kitahara ◽

K. Aoshima ◽

J. Tsutsumi ◽

H. Minemawari ◽

S. Arai ◽

...

Keyword(s):

Thin Film ◽

Dielectric Layer ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Low Voltage ◽

Organic Thin Film Transistors ◽

Base Layer ◽

Organic Thin Film ◽

Low Voltage Operation ◽

Silver Electrodes

ABSTRACTRecently, an epoch-making printing technology called “SuPR-NaP (Surface Photo-Reactive Nanometal Printing)” that allows easy, high-speed, and large-area manufacturing of ultrafine silver wiring patterns has been developed. Here we demonstrate low-voltage operation of organic thin-film transistors (OTFTs) composed of printed source/drain electrodes that are produced by the SuPR-NaP technique. We utilize an ultrathin layer of perfluoropolymer, Cytop, that functions not only as a base layer for producing patterned reactive surface in the SuPR-NaP technique but also as an ultrathin gate dielectric layer of OTFTs. By the use of 22 nm-thick Cytop gate dielectric layer, we successfully operate polycrystalline pentacene OTFTs below 2 V with negligible hysteresis. We also observe the improvement of carrier injection by the surface modification of printed silver electrodes. We discuss that the SuPR-NaP technique allows the production of high-capacitance gate dielectric layers as well as high-resolution printed silver electrodes, which provides promising bases for producing practical active-matrix OTFT backplanes.

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Threshold Voltage Instability of Top Gate Single-Crystalline Si Thin-film Transistors on Flexible Substrate Using SiO as Gate Dielectric

ECS Meeting Abstracts ◽

10.1149/ma2007-01/15/723 ◽

2007 ◽

Keyword(s):

Thin Film ◽

Threshold Voltage ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Flexible Substrate ◽

Single Crystalline ◽

Voltage Instability ◽

Si Thin Film

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Fabricaton Ofactive Devices and Logic Gates on Fibers

MRS Proceedings ◽

10.1557/proc-769-h8.6 ◽

2003 ◽

Vol 769 ◽

Author(s):

YongWoo Choi ◽

Ioannis Kymissis ◽

Annie Wang ◽

Akintunde I. Akinwande

Keyword(s):

Threshold Voltage ◽

Electronic Structures ◽

Low Cost ◽

Logic Gates ◽

Wearable Electronics ◽

Drain Voltage ◽

Large Area ◽

Active Devices ◽

P Type ◽

A Current

AbstractTextiles are a suitable substrate for large area, flexible and wearable electronics because of their excellent flexibility, mechanical properties and low cost manufacturability. The ability to fabricate active devices on fiber is a key step for achieving large area and flexible electronic structures. We fabricated transistors and inverters with a-Si film and pentacene film on Kapton film and cut them into fibers. The a-Si TFT showed a threshold voltage of 8.5 V and on/off ratio of 103 at a drain voltage of 10 V. These are similar to the characteristics of a TFT fabricated on a glass substrate at the same time. The maximum gain of the inverter with an enhancement n-type load was 6.45 at a drain voltage of 10 V. The pentacene OTFT showed a threshold voltage of -8 V and on/off ratio of 103 at a drain voltage of -30 V. The inverter with a depletion p-type load showed a voltage inversion but the inversion occurred at the wrong voltage. The antifuse was successfully programmed with a voltage pulse and also a current pulse. The resistance decreased from 10 GΩ to 2 kΩ after the programming.

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Inkjet-Printed Top-Gate Thin-Film Transistors Based on InGaSnO Semiconductor Layer with Improved Etching Resistance

Coatings ◽

10.3390/coatings10040425 ◽

2020 ◽

Vol 10 (4) ◽

pp. 425 ◽

Cited By ~ 1

Author(s):

Siting Chen ◽

Yuzhi Li ◽

Yilong Lin ◽

Penghui He ◽

Teng Long ◽

...

Keyword(s):

Thin Film ◽

Metal Oxide ◽

Dielectric Layer ◽

Thin Film Transistors ◽

Gate Dielectric ◽

Acid Resistance ◽

Semiconductor Layer ◽

Sn Doping ◽

First Time

Inkjet-printed top-gate metal oxide (MO) thin-film transistors (TFTs) with InGaSnO semiconductor layer and carbon-free aqueous gate dielectric ink are demonstrated. It is found that the InGaO semiconductor layer without Sn doping is seriously damaged after printing aqueous gate dielectric ink onto it. By doping Sn into InGaO, the acid resistance is enhanced. As a result, the printed InGaSnO semiconductor layer is almost not affected during printing the following gate dielectric layer. The TFTs based on the InGaSnO semiconductor layer exhibit higher mobility, less hysteresis, and better stability compared to those based on InGaO semiconductor layer. To the best of our knowledge, it is for the first time to investigate the interface chemical corrosivity of inkjet-printed MO-TFTs. It paves a way to overcome the solvent etching problems for the printed TFTs.

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