Phonon-drag Contribution to Seebeck Coefficient of Ge-on-insulator Substrate Fabricated by Wafer Bonding Process

We investigate thermoelectric characteristics of SiGe nanostructures for realizing high-sensitive infrared photodetector applications. In this paper, for future Ge and SiGe nanowires, we fabricate p-type Ge-on-insulator (GOI) substrates by a direct wafer bonding process. We discuss the annealing effect on the GOI substrate in the process and measure its Seebeck coefficient in the temperature range of 290-350 K. The Seebeck coefficient of the GOI layers is almost identical with the reported values for Ge. This result confirms that the measured Seebeck coefficient of GOI layers is not influenced by the buried oxide (BOX) layer and the Si substrate.

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Two-dimensional X-ray waveguides: fabrication by wafer-bonding process and characterization

Applied Physics A ◽

10.1007/s00339-007-4374-1 ◽

2008 ◽

Vol 91 (1) ◽

pp. 7-12 ◽

Cited By ~ 4

Author(s):

A. Kohlstedt ◽

S. Kalbfleisch ◽

T. Salditt ◽

M. Reiche ◽

U. Gösele ◽

...

Keyword(s):

Wafer Bonding ◽

Bonding Process ◽

Two Dimensional ◽

X Ray

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Study on Phonon Drag Effect and Phonon Transport in Thin Si-on-Insulator Layers

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.1117.86 ◽

2015 ◽

Vol 1117 ◽

pp. 86-89 ◽

Cited By ~ 1

Author(s):

Hiroya Ikeda ◽

Takuro Oda ◽

Yuhei Suzuki ◽

Yoshinari Kamakura ◽

Faiz Salleh

Keyword(s):

Seebeck Coefficient ◽

Carrier Concentration ◽

Phonon Scattering ◽

Phonon Transport ◽

Infrared Photodetector ◽

Phonon Drag ◽

Drag Effect ◽

Phonon Modes ◽

Highly Sensitive ◽

Insulator Layers

The Seebeck coefficient of P-doped ultrathin Si-on-insulator (SOI) layers is investigated for the application to a highly-sensitive thermopile infrared photodetector. It is found that the Seebeck coefficient originating from the phonon drag is significant in the lightly doped region and depends on the carrier concentration with increasing carrier concentration above ~5×1018 cm-3. On the basis of Seebeck coefficient calculations considering both electron and phonon distribution, the phonon-drag part of SOI Seebeck coefficient is mainly governed by the phonon transport, in which the phonon-phonon scattering process is dominant rather than the crystal boundary scattering even in the SOI layer with a thickness of 10 nm. This fact suggests that the phonon-drag Seebeck coefficient is influenced by the phonon modes different from the thermal conductivity.

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Technologies for Wafer Level MEMS Capping based on Permanent and Temporary Wafer Bonding

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2015dpc-tp31 ◽

2015 ◽

Vol 2015 (DPC) ◽

pp. 000698-000725 ◽

Cited By ~ 1

Author(s):

Kai Zoschke ◽

Klaus-Dieter Lang

Keyword(s):

Wafer Bonding ◽

Rf Mems ◽

Electrical Contacts ◽

Bonding Process ◽

Frame Structure ◽

Back Side ◽

Wafer Level ◽

Free Standing ◽

Carrier Wafer ◽

Base Substrate

Further cost reduction and miniaturization of electronic systems requires new concepts for highly efficient packaging of MEMS components like RF resonators or switches, quartz crystals, bolometers, BAWs etc. This paper describes suitable base technologies for the miniaturized, low-cost wafer level chip-scale packaging of such MEMS. The approaches are based on temporary handling and permanent bonding of cap structures using adhesives or solder onto passive or active silicon wafers which are populated with MEMS components or the MEMS wafer themselves. Firstly, an overview of the possible packaging configurations based on different types of MEMS is discussed where TSV based and non-TSV based packaging solutions are distinguished in general. The cap structure for the TSV based solution can have the same size as the MEMS carrying substrate, since the electrical contacts for the MEMS can be routed either thought the cap or base substrate. Thus, full format cap wafers can be used in a regular wafer to wafer bonding process to create the wafer level cavity packages. However, if no TSVs are present in the cap or base substrate, the cap structure needs to be smaller than the base chip, so that electrical contacts outside the cap area can be accessed after the caps were bonded. Such a wafer level capping with caps smaller than the corresponding base chips can be obtained in two ways. The first approach is based on fabrication and singulation of the caps followed by their temporary face up assembly in the desired pattern on a help wafer. In a subsequent wafer to wafer bonding sequence all caps are transferred onto the base wafer. Finally the help wafer is removed from the back side of the bonded caps. This approach of reconfigured wafer bonding is especially used for uniform cap patterns or, if MEMS have an own bond frame structure. In that case no additional cap is required, since the MEMS can act as their own cap. The second approach is based on cap structure fabrication using a compound wafer stack consisting of two temporary bonded wafers. One wafer acts as carrier wafer whereas the other wafer is processed to form cap structures. Processes like thinning, silicon dry etching, deposition and structuring of polymer or metal bonding frames are performed to generate free-standing and face-up directed cap structures. The so created “cap donor wafer” is used in a wafer to wafer bonding process to bond all caps permanently to the corresponding MEMS base wafer. Finally, the temporary bonded carrier wafer is removed from the backside of the transferred caps. With that approach a fully custom specific and selective wafer level capping is possible featuring irregular cap patterns and locations on the MEMS base wafer. Examples like the selective capping process for RF MEMS switches are presented and discussed in detail. All processes were performed at 200mm wafer level.

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TLP Bonding Technologies for Micro Joining and 3D Packaging

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2010dpc-wa12 ◽

2010 ◽

Vol 2010 (DPC) ◽

pp. 001221-001252 ◽

Cited By ~ 1

Author(s):

Kei Murayama ◽

Mitsuhiro Aizawa ◽

Mitsutoshi Higashi

Keyword(s):

High Temperature ◽

Melting Point ◽

Low Temperature ◽

Wafer Bonding ◽

Bonding Process ◽

Tlp Bonding ◽

Hermetic Sealing ◽

Low Temperature Bonding ◽

Free Material ◽

Bonding Technique

The bonding technique for High density Flip Chip(F.C.) packages requires a low temperature and a low stress process to have high reliability of the micro joining ,especially that for sensor MEMS packages requires hermetic sealing so as to ensure their performance. The Transient Liquid Phase (TLP) bonding, that is a kind of diffusion bonding is a technique that connects the low melting point material such as Indium to the higher melting point metal such as Gold by the isothermal solidification and high-melting-point intermetallic compounds are formed. Therefore, it is a unique joining technique that can achieve not only the low temperature bonding and also the high temperature reliability. The Gold-Indium TLP bonding technique can join parts at 180 degree C and after bonding the melting point of the junction is shifted to more than 495 degree C, therefore itfs possible to apply the low temperature bonding lower than the general use as a lead free material such as a SAC and raise the melting point more than AuSn solder which is used for the high temperature reliability usage. Therefore, the heat stress caused by bonding process can be expected to be lowered. We examined wafer bonding and F.C bonding plus annealing technique by using electroplated Indium and Gold as a joint material. We confirmed that the shear strength obtained at the F.C. bonding plus anneal technique was equal with that of the wafer bonding process. Moreover, it was confirmed to ensure sufficient hermetic sealing in silicon cavity packages that had been bonded at 180 degree C. And the difference of the thermal stress that affect to the device by the bonding process was confirmed. In this paper, we report on various possible application of the TLP bonding.

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Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/2012dpc-wp13 ◽

2012 ◽

Vol 2012 (DPC) ◽

pp. 1-24

Author(s):

Michael Gallagher ◽

Jong-Uk Kim ◽

Eric Huenger ◽

Kai Zoschke ◽

Christina Lopper ◽

...

Keyword(s):

Low Temperature ◽

Wafer Bonding ◽

Flip Chip ◽

Bonding Temperature ◽

Bonding Process ◽

Curing Temperature ◽

Wafer Level ◽

Mechanical Adhesion ◽

3D Stacking ◽

Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

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