scholarly journals Understanding Jig Alignment Error Occurrences for Substrate 1-Map Strips

2021 ◽  
pp. 113-118
Author(s):  
Mariane A. Mendoza ◽  
Maria Virginia S. Buera ◽  
Frederick Ray I. Gomez ◽  
Allen Jay D. Kumawit
Keyword(s):  
Semiconductor Industry ◽  
High Volume ◽  
Single Units ◽  
Alignment Error ◽  
Upstream Process ◽  
Alignment Errors

Singulation is a process in a semiconductor industry where high dense strips were singulated into single units. Jig saw singulation was the updated technology where strips were seated and vacuumed on a rubber nest jig during singulation. Jig saw singulation is also practical for high volume manufacturing as it demands minimal indirect materials. To cut the strips, jig alignment with the strip was measured by the machine to ensure that the rubber nest jig will not be cut and damaged while the strip is being singulated. However, with the different upstream process that the strip undergone, machine prompt frequent jig alignment errors when the machine detected that the strip saw street has high displacement with the recorded alignment of the saw street of rubber nest jig. Through this study, the authors have driven to understand the jig alignment errors occurrences as well as the assistance that can be made for the strip to be processed. The authors also included the study of the risks that might be imposed on both rubber nest jig and the affected strips, as well as the recommendations when jig alignment errors were encountered.

scholarly journals The Estimation of Angular Misalignments for Ultra Short Baseline Navigation Systems. Part II: Experimental Results

2013 ◽  
Vol 66 (5) ◽  
pp. 773-787 ◽  
Author(s):  
Hsin-Hung Chen
Keyword(s):  
Trial Data ◽  
Experimental Results ◽  
Experimental Result ◽  
Alignment Error ◽  
Navigation Systems ◽  
Analytical Prediction ◽  
Short Baseline ◽  
Sea Trial ◽  
Alignment Errors ◽  
Cross Track

An algorithm of alignment calibration for Ultra Short Baseline (USBL) navigation systems was presented in the companion work (Part I). In this part (Part II) of the paper, this algorithm is tested on the sea trial data collected from USBL line surveys. In particular, the solutions to two practical problems referred to as heading deviation and cross-track error in the USBL line survey are presented. A field experiment running eight line surveys was conducted to collect USBL positioning data. The numerical results for the sea trial data demonstrated that the proposed algorithm could robustly and effectively estimate the alignment errors. Comparisons of the experimental result with the analytical prediction of roll misalignment estimation in Part I is drawn, showing good agreement. The experimental results also show that an inappropriate estimation of roll alignment error will significantly degrade the quality of estimations of heading and pitch alignment errors.

Error Analysis by Square 3 x 3 Machining Method for Five-Axis Machining Centers

2020 ◽  
Author(s):  
Shigehiko Sakamoto ◽  
Atsushi Yokoyama ◽  
Kazumasa Nakayasu ◽  
Toshihiro Suzuki ◽  
Shinji Koike
Keyword(s):  
International Standards ◽  
Test Method ◽  
Accuracy Evaluation ◽  
Alignment Error ◽  
Machined Surface ◽  
Machining Center ◽  
Alignment Errors ◽  
Assembly Error ◽  
Five Axis ◽  
Machined Surfaces

Abstract The establishment of international standards for 5-axis control machining centers has been supported by the high interest of each country. Internationally, various accuracy inspection methods have been proposed and widely discussed. Accuracy measuring devices for these purposes have also been proposed. In 2014, inspection methods for 5-axis machines were published in ISO 10791-6 and 10791-7. In this research, we propose a test method to process 9 square faces as a new accuracy evaluation method. We simulate the influence of assembly error by the proposed square 3 × 3 machining method on the machined surface. By processing 9 square faces with different tool angle on the same plane, it was possible to evaluate the influence of assembly errors in the 5-axis machining center on the machined surface. Nine surfaces machined by the square 3 × 3 processing method cause differences in surface height due to alignment errors. In addition, nine machined surfaces become all diagonal not parallelism. The alignment errors of the 5-axis machining center is identified by evaluating the orientation of the machined surfaces. Specifically, we propose a newly method to measure the height difference of nine surfaces. Then, the possibility of identifying the alignment error of the 5-axis machining center using the measurement results is shown.

3D Technology Applications Market Trends & Key Challenges

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000363-000400
Author(s):  
Thibault Buisson ◽  
Amandine Pizzagalli ◽  
Eric Mounier ◽  
Rozalia Beica
Keyword(s):  
Supply Chain ◽  
Business Models ◽  
Semiconductor Industry ◽  
High Volume ◽  
Advanced Technology ◽  
Passive Component ◽  
Process Technology ◽  
3D Integration ◽  
3D Technology ◽  
Major Player

Semiconductor industry, for more than four decades, has rigorously followed Moore's Law in scaling down the CMOS technologies. Although several new materials and processes are being developed to address the challenges of future technology nodes, in the coming years they will be limited with respect to functionalities that future devices will require. As a consequence a clear trend of moving from CMOS to package and system architecture can be observed. Three-dimensional (3D) technology using the well-known Through Silicon Via (TSV) interconnect is one the emerging option, considered today the most advanced technology, that could enable various heterogeneous integration. Indeed such technology is not limited to the CMOS scaling in itself, it is rather based on bringing more functionalities by stacking different type of devices (Logic, Memory, Analog, MEMS, Passive component...) while reducing the form factor of the packaging. This functional diversification is also known as More-than-Moore. In addition, considering Known Good Die approach, each component of the 3D package could have a different manufacturer using different wafer sizes and node technology, thus bringing more complexity but also more opportunities and responsibilities to the supply chain. There are several business models identified, either using vertical integration or collaborative approach, if a dominant one will emerge or several tactics will co-exist, it is still remains a key question that need to be answered. The supply chain interaction and key players will be addressed in this presentation, including current and future standardization needs. This is today a key for the manufacturing of advanced 3D devices. 3D integration is considered today a new paradigm for the semiconductor industry, since it will drive evolution for packages for the coming decades. Due to several advantages that TSV technology can bring, several platforms have started. 3D WLCSP, 2.5D interposers & 3DIC are the main platforms that will be studied in this paper. Market forecasts in terms of wafer starts, market revenue, segments and end-products as well as supply chain activities and major player interactions will be presented. The industry has enthusiastically been waiting for mass production of 3D ICs. Although some small level of production has already been reported, the adoption rate in high volume manufacturing (HVM) is still low due to unresolved challenges that the industry still needs to address. Process technology is not fully mature, there are still many challenges in bonding and de-bonding, testing as well as thermal management that have to be overcome. Furthermore, design tools have to be fully released to enable proper 3D integration design. Looking at the time to market it is foreseen that device such as the Hybrid Memory Cube, combining high-speed logic with a multiple stacks of TSV bonded memories, will come into high volume production in 2014. This will definitely change the world of the memory market and will significantly speed up the adoption of 3D technologies. Technology roadmaps for 3D integration will also be included in the manuscript and reviewed during the presentation.

Increased High-Temperature Reliability and Package Hardening of Commercial Integrated Circuits (Through Die Extraction, Electroless Nickel/Gold Pad Reconditioning, and Ceramic Re-Assembly)

2015 ◽  
Vol 2015 (HiTEN) ◽  
pp. 000123-000128
Author(s):  
Erick M. Spory
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
Semiconductor Industry ◽  
Value Added ◽  
Electroless Nickel ◽  
High Volume ◽  
Gold Plating ◽  
Global Circuit ◽  
Temperature Applications

There is an ever-increasing demand for electronics in higher temperature applications, both in variety and volume. In many cases, the actual integrated circuit within the plastic packaging can support operation at higher temperatures, although the packaging and connectivity is unable to do so. Ultimately, there still remains a significant gap in the volume demand required for high temperature integrated circuit lines to justify support of more expensive ceramic solutions by the original component manufacturer vs. the cheaper, high-volume PEM flows. Global Circuit Innovations, Inc. has developed a manufacturable, cost-effective solution to extract the integrated circuit from any plastic encapsulated device and subsequently re-package that device into an identical ceramic footprint, with the ability to maintain high-integrity connectivity to the device and enabling functionality for 1000's of hours at temperatures at 250C and beyond. This process represents a high-value added solution to provide high-temperature integrated circuits for a large spectrum of requirements: low-volume, quick-turn evaluation of integrated circuit prototyping, as well as medium to high-volume production needs for ongoing production needs. Although both die extraction and integrated circuit pad electroless nickel/gold plating have both been performed successfully for many years in the semiconductor industry, Global Circuit Innovations, Inc. has been able to combine the two in a reliable, volume manufacturing flow to satisfy many of the stringent requirements for high-temperature applications.

scholarly journals Lithography for enabling advances in integrated circuits and devices

2012 ◽  
Vol 370 (1973) ◽  
pp. 4015-4041 ◽  
Author(s):  
C. Michael Garner
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Extreme Ultraviolet ◽  
Field Effect Transistors ◽  
Semiconductor Industry ◽  
High Volume ◽  
Pattern Transfer ◽  
Time Pattern ◽  
Technology Roadmap ◽  
The Future

Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

scholarly journals A Prospective Study to Investigate the Placement of Setup Skin Markings for Larger Breasted Women Undergoing External Beam Radiotherapy (RT) for Breast Cancer

2019 ◽  
pp. 99-122
Author(s):  
Chris Osam Doudoo ◽  
Neill Roberts ◽  
Emmanuel Amankwaa Frempong ◽  
Clement Edusa ◽  
Kwamena Beecham ◽  
...  
Keyword(s):  
Breast Cancer ◽  
External Beam Radiotherapy ◽  
Systematic Errors ◽  
Patient Treatment ◽  
P Value ◽  
Alignment Error ◽  
External Beam ◽  
Significant Difference ◽  
Portal Images ◽  
Alignment Errors

Background: The technique of placing all three skin marks (reference skin marks) on a single position during CT simulation for setup of patients undergoing conventional breast radiotherapy becomes a challenge when presented with larger breasted women (bra cup size ≥ D). A new way of using skin marks in setting these patients up has been developed where three skin marks are made on the patient (one on the sternum and two lateral skin marks more inferiorly beneath the breasts) for setup as against the departmental standard of using only a single skin mark on the sternum, and employing an SSD (Source to Skin Distance) technique. This study therefore reviewed the placement of the skin markings for larger breasted women undergoing external beam radiotherapy for breast cancer by quantifying treatment field alignment errors and setup errors between the two different setup techniques. Method: 36 patients were used in this study. Out of this number, 18 were setup using three reference skin marks and the remaining 18 were setup using one reference anterior skin mark. With an acceptable patient treatment field alignment error of 2 degrees, portal images (AP and lateral) of the different skin mark techniques were analysed for field alignment errors using an Iview GT system. More so, portal images (AP and lateral) of setup for both techniques were analysed for systematic (Σ) and random (σ) errors. Results:The AP images of the single skin mark setup and the three skin mark setup yielded no significant difference as they recorded a p- value (p<0.05) of 0.089 and 0.110 respectively when compared to the treatment field alignment threshold error of 2 degrees. The lateral images of the three skin mark also yielded no significant difference as a p- value (p<0.05) of 0.091 was recorded. The lateral images of the single skin mark yielded a significant difference with a p- value (p<0.05) of 0.026. Secondly, mean comparisons of the field alignment errors between the two setup techniques yielded no significant difference in the AP images as a p- value (p<0.05) of 0.089 was detected. On the contrary, a p- value (p<0.05) of 0.026 was recorded in the field alignment errors of the lateral images. This difference is significant. Lastly, random errors were reduced in all directions (AP- anterior-posterior, SI- superior-inferior and LR- Left-right) in the three skin mark setup (4.5mm AP, 4.9mm SI and 2.4mm LR) as compared to the single skin mark setup (4.7mm AP, 5.2mm SI and 2.6mm LR). Systematic errors were also reduced in the three skin mark setup (1.7mm AP and 1.8mm SI) compared to the single skin mark setup (2.0mm AP, 2.1mm SI). Systematic errors in the LR direction on the other hand increased from 2.0mm in the single skin mark to 2.2mm in the three skin marks. Conclusion For setup of larger breasted women undergoing external beam radiotherapy for breast cancer, the three skin mark setup technique is superior to the single skin mark setup technique.

SiP: Bringing Ideas to High Volume Reality

2015 ◽  
Vol 2015 (S2) ◽  
pp. S1-S35
Author(s):  
Rich Rice
Keyword(s):  
Form Factor ◽  
Product Space ◽  
Semiconductor Industry ◽  
Electronic Markets ◽  
High Volume ◽  
Vast Number ◽  
Revenue Growth ◽  
Growth System ◽  
Market Needs

The semiconductor industry has entered a phase of accelerating integration, on both the corporate and product fronts. Companies must provide integrated solutions to end electronic markets to maintain their business channels and revenue growth. System-in-Package (SiP) provides an avenue for product designers to increase functionality while reducing form factor, which are absolute requirements for a vast number of applications particularly in the mobile product space. This presentation will cover the industry landscape, and highlight the key packaging technologies to be deployed in coming years to enable semiconductor and electronic companies meet evolving market needs.

Key Technology of Construction Control of the Middle Pylon of Taizhou Bridge

2012 ◽  
Vol 446-449 ◽  
pp. 1138-1143
Author(s):  
Ning Yang ◽  
Xin Peng You ◽  
Yong Tao Zhang
Keyword(s):  
Yangtze River ◽  
Suspension Bridge ◽  
General Construction ◽  
Construction Control ◽  
Alignment Error ◽  
Key Technology ◽  
Whole Process ◽  
Construction Procedure ◽  
Control Concept ◽  
Alignment Errors

The Taizhou Yangtze river bridge is a suspension bridge with three pylons and two 1080m long navigation spans. The middle pylon with height 191.5m is made of steel. The general construction procedure of the middle steel pylon is briefly introduced. Construction control of the pylon is carried out during the whole process of the construction. The control concept is extended to the manufacture stage besides the installation stage. The manufacturing alignment errors are strictly controlled in precast process of the segments in factory, and the alignment error is identified and predicted precisely during the installation stage. The adjusting joints are adopted to adjust the accumulated errors, which ensure that the steel pylon alignment could satisfy the as-built precision requirements.

Physical Chemistry of Water Droplets in Wafer Cleaning with Low Water Use

2014 ◽  
Vol 219 ◽  
pp. 134-137
Author(s):  
Jacques C.J. van der Donck ◽  
Jurrian Bakker ◽  
Jeroen A. Smeltink ◽  
Robin B.J. Kolderweij ◽  
Ben C.M.B. van der Zon ◽  
...  
Keyword(s):  
Physical Chemistry ◽  
Energy Consumption ◽  
Water Use ◽  
Semiconductor Industry ◽  
Pure Water ◽  
High Volume ◽  
Mechanical Action ◽  
Feature Size ◽  
Ultra Pure Water ◽  
Wafer Cleaning

Reduction of water and energy consumption is of importance for keeping viable industry in Europe. In 2012 the Eniac project Silver was started in order to reduce water and energy consumption in the semiconductor industry by 10% [1]. Cleaning of wafers is one of the key process steps that require a high volume of Ultra-Pure Water (UPW). For the production of a single wafer more than 120 cleaning steps may be required [2]. Furthermore, the reduction of the feature size makes devices more vulnerable to damage by mechanical action. This trend gives rise to the need for new, gentler cleaning processes.

scholarly journals Alignment Error Models and Ensemble-Based Data Assimilation

2005 ◽  
Vol 133 (6) ◽  
pp. 1687-1709 ◽  
Author(s):  
W. Gregory Lawson ◽  
James A. Hansen
Keyword(s):  
Minimum Variance ◽  
Error Model ◽  
Alignment Error ◽  
Error Models ◽  
Wide Range ◽  
Estimation Problems ◽  
Estimation Scheme ◽  
Non Gaussian ◽  
The Individual ◽  
Alignment Errors

Abstract The concept of alternative error models is suggested as a means to redefine estimation problems with non-Gaussian additive errors so that familiar and near-optimal Gaussian-based methods may still be applied successfully. The specific example of a mixed error model including both alignment errors and additive errors is examined. Using the specific form of a soliton, an analytical solution to the Korteweg–de Vries equation, the total (additive) errors of states following the mixed error model are demonstrably non-Gaussian for large enough alignment errors, and an ensemble of such states is handled poorly by a traditional ensemble Kalman filter, even if position observations are included. Consideration of the mixed error model itself naturally suggests a two-step approach to state estimation where the alignment errors are corrected first, followed by application of an estimation scheme to the remaining additive errors, the first step aimed at removing most of the non-Gaussianity so the second step can proceed successfully. Taking an ensemble approach for the soliton states in a perfect-model scenario, this two-step approach shows a great improvement over traditional methods in a wide range of observational densities, observing frequencies, and observational accuracies. In cases where the two-step approach is not successful, it is often attributable to the first step not having sufficiently removed the non-Gaussianity, indicating the problem strictly requires an estimation scheme that does not make Gaussian assumptions. However, in these cases a convenient approximation to the two-step approach is available, which trades obtaining a minimum variance estimate ensemble mean for more physically sound updates of the individual ensemble members.

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