scholarly journals Design of a Voltage to Time Converter with High Conversion Gain for Reliable and Secure Autonomous Vehicles

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 384
Author(s):  
Nandakishor Yadav ◽  
Youngbae Kim ◽  
Mahmoud Alashi ◽  
Kyuwon Ken Choi
Keyword(s):  
Autonomous Vehicles ◽  
High Speed ◽  
Input Voltage ◽  
High Conversion ◽  
Conversion Gain ◽  
Analog To Digital ◽  
Voltage Range ◽  
Bias Temperature Instability ◽  
High Speed Design ◽  
On Chip

Automation of vehicles requires a secure, reliable, and real-time on-chip system. These systems also require very high-speed and compact on-chip analog to digital converters (ADC). The conventional ADC cannot fulfill this requirement. In this paper, we proposed a Darlington pair- and source biasing-based high speed, secure, and reliable voltage to time converter (VTC). It is a compact, high-speed design and gives high conversion gain. The source biasing also helps to increase the input voltage range. The conversion gain of the proposed circuit is 101.43ns/v, which is 52 times greater than the gain achieved by state-of-the-art design. It also shows less effect of process variation and bias temperature instability.

A Compact High-Performance 10-bit 30-Channel OLED Driver Using Switched Capacitor Circuit for High-Linearity Application

2021 ◽  
pp. 2250013
Author(s):  
Neeru Agarwal ◽  
Neeraj Agarwal ◽  
Chih-Wen Lu
Keyword(s):  
Power Consumption ◽  
Output Voltage ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Cmos Technology ◽  
Settling Time ◽  
Switched Capacitor ◽  
Voltage Range ◽  
High Output Voltage

This work proposes a new OLED driver architecture with 10-bit segmented DAC and switched capacitor multiply-by-two circuit application. A 30-channel 10-bit switched capacitor driver chip prototype is implemented in 0.18-[Formula: see text]m CMOS technology. In this architecture, the achieved output range is 1.5–4.8[Formula: see text]V for an input range of 1.5–3.15[Formula: see text]V, which is suitable for OLED driver with different colors. This architecture is not only converting the digital input signal to analog output for the display panel but also giving amplified high output voltage range. In the segmented DAC, 6-bit coarse DAC and 4-bit fine DAC are used for the input voltage range 1.5–3.15[Formula: see text]V. In a conventional RDAC for the output voltage of 4.8[Formula: see text]V, it requires 2[Formula: see text] switches i.e., 14-bit RDAC for the same resolution. Hence, conventional RDAC driver is four times larger than the proposed innovative very compact and high speed 10-bit segmented DAC switched capacitor OLED driver. The new architecture drastically reduces the number of switches and complex metal routing which results in reduced power consumption and good settling time. In the proposed OLED driver, no extra buffer is required as switched capacitor op-amp is applied for the same purpose with a gain of more than one. This high-resolution design with small die area also improves the linearity and uniformity with low-power consumption. The post-simulated results show that the OLED driver exhibits the maximum DNL and INL of 0.03 LSB and [Formula: see text]0.06 LSB, respectively, with an LSB voltage of 3[Formula: see text]mV. The one-channel area is 0.586[Formula: see text]mm [Formula: see text] 0.017[Formula: see text]mm and the settling time is 4.25[Formula: see text][Formula: see text]s for 30[Formula: see text]k[Formula: see text] and 30[Formula: see text]pF driving load.

Thermometer to Gray Encoders

2015 ◽  
pp. 323-335
Author(s):  
Yogendra Gupta ◽  
Sandeep Saini
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Gray Code ◽  
Direct Conversion ◽  
Flash Adc ◽  
Analog To Digital ◽  
Modulation Techniques ◽  
On Chip ◽  
Minimal Area

Analog to Digital Converter (ADC) is a key functional block in the design of mixed signal, system on chip, and signal processing applications. An optimized method for the direct conversion of analog signal to Gray code representation is presented. This eliminates the need for binary-to-Gray code conversion in many digital modulation techniques like M-PSK and M-QAM, which uses Gray coding representation to represent the symbols that are modulated. The authors design a low-power and high-speed Thermometer to Gray encoder for Flash ADC, as encoders have been widely utilized in high-performance critical applications which persistently impose special design constraints in terms of high-frequency, low power consumption, and minimal area. In this chapter, they propose a new circuit that converts the Thermometer code to Gray code and also yields minimized power.

A Survey Addressing on High Performance On-Chip VLSI Interconnect

2013 ◽  
Vol 59 (3) ◽  
pp. 307-312 ◽  
Author(s):  
C. Mohamed Yousuff ◽  
V. Mohamed Yousuf Hasan ◽  
M. R. Khan Galib
Keyword(s):  
Communication Systems ◽  
High Speed ◽  
High Performance ◽  
State Of The Art ◽  
Vlsi Circuits ◽  
Cmos Circuits ◽  
Delay Optimization ◽  
High Speed Design ◽  
On Chip ◽  
Very High

Abstract With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.

scholarly journals 92.5% Average Power Efficiency Fully Integrated Floating Buck Quasi-Resonant LED Drivers Using GaN FETs

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 575
Author(s):  
Mei Yu Soh ◽  
S. Lawrence Selvaraj ◽  
Lulu Peng ◽  
Kiat Seng Yeo
Keyword(s):  
Integrated Circuit ◽  
Power Efficiency ◽  
Average Power ◽  
Input Voltage ◽  
Led Driver ◽  
Fully Integrated ◽  
Voltage Range ◽  
Percentage Improvement ◽  
On Chip ◽  
Led Drivers

LEDs are highly energy efficient and have substantially longer lifetimes compared to other existing lighting technologies. In order to facilitate the new generation of LED devices, approaches to improve power efficiency with increased integration level for lighting device should be analysed. This paper proposes a fully on-chip integrated LED driver design implemented using heterogeneous integration of gallium nitride (GaN) devices atop BCD circuits. The performance of the proposed design is then compared with the conventional fully on-board integration of power devices with the LED driver integrated circuit (IC). The experimental results confirm that the fully on-chip integrated LED driver achieves a consistently higher power efficiency value compared with the fully on-board design within the input voltage range of 4.5–5.5 V. The maximal percentage improvement in the efficiency of the on-chip solution compared with the on-board solution is 18%.

scholarly journals DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH

2012 ◽  
pp. 51-56
Author(s):  
CHANNAKKA LAKKANNAVAR ◽  
SHRIKANTH K. SHIRAKOL ◽  
KALMESHWAR N. HOSUR
Keyword(s):  
Data Storage ◽  
High Speed ◽  
Digital Signal ◽  
Building Blocks ◽  
Input Voltage ◽  
Cmos Technology ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Flash Adc ◽  
Analog To Digital

Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.

A High Resolution Single Slope ADC with Low Operation Speed for Uncooled Infrared Focal Plane Array

2014 ◽  
Vol 513-517 ◽  
pp. 4551-4554
Author(s):  
Long Cheng Que ◽  
Lin Hai Wei ◽  
Jian Lv ◽  
Ya Dong Jiang
Keyword(s):  
High Resolution ◽  
Focal Plane ◽  
High Speed ◽  
Infrared Imaging ◽  
Focal Plane Array ◽  
Infrared Focal Plane Array ◽  
Analog To Digital ◽  
Operation Speed ◽  
Conventional Structure ◽  
On Chip

Due to the advantages of the uncooled infrared focal plane array (UIFPA), it is widely used in various fields. To achieve more vivid image, the dimensions of infrared focal plane array need to be enlarged. Hence the high speed analog to digital converter (ADC) integrated on-chip needs to obtain the digital infrared imaging signal. We propose a new single slope ADC with half-period counter and two ramp generators to realize the high resolution digitizing, which can operate at much lower speed. The operation speed of this proposed single slope ADC can be decreased to the 25% of the conventional structure while the static characteristics are still good.

Multi-functional D-bandI/Qmodulator/demodulator MMICs in SiGe BiCMOS technology

2018 ◽  
Vol 10 (5-6) ◽  
pp. 596-604 ◽  
Author(s):  
Sona Carpenter ◽  
Zhongxia Simon He ◽  
Herbert Zirath
Keyword(s):  
High Speed ◽  
Phase Shifter ◽  
Intermediate Frequency ◽  
Local Oscillator ◽  
Conversion Gain ◽  
Error Vector Magnitude ◽  
Bicmos Technology ◽  
Sige Bicmos ◽  
On Chip ◽  
Image Rejection Ratio

AbstractThis paper presents the design and characterization of a D-band (110–170 GHz) monolithic microwave integrated direct carrier quadrature modulator and demodulator circuits with on-chip quadrature local oscillator (LO) phase shifter and radio frequency (RF) balun fabricated in a 130 nm SiGe BiCMOS process withft/fmaxof 250 GHz/400 GHz. These circuits are suitable for low-power ultra-high-speed wireless communication and can be used in both homodyne and heterodyne architectures. In single-sideband operation, the modulator demonstrates a maximum conversion gain of 9.8 dB with 3-dB RF bandwidth of 33 GHz (from 119 GHz to 152 GHz). The measured image rejection ratio (IRR) and LO suppression are 19 dB and 31 dB, respectively. The outputP1dBis −4 dBm at 140 GHz RF and 1 GHz intermediate frequency (IF) and the chip consumes 53 mW dc power. The demodulator, characterized as an image reject mixer, exhibits 10 dB conversion gain with 23-dB IRR. The measured 3-dB RF bandwidth is 36 GHz and the IF bandwidth is 18 GHz. The active area of both the chips is 620 µm × 480 µm including the RF and LO baluns. A 12-Gbit/s QPSK data transmission using 131-GHz carrier signal is demonstrated on modulator with measured modulator-to-receiver error vector magnitude of 21%.

The bright future of digital imaging in scanning electron microscopy

1993 ◽  
Vol 51 ◽  
pp. 768-769
Author(s):  
M. T. Postek ◽  
A. E. Vladar
Keyword(s):  
Electron Microscopy ◽  
Scanning Electron Microscopy ◽  
Digital Imaging ◽  
High Speed ◽  
High Performance ◽  
Mass Storage ◽  
Analog To Digital ◽  
Central Processing ◽  
Digital Imaging Technology ◽  
Scanning Electron

One of the major advancements applied to scanning electron microscopy (SEM) during the past 10 years has been the development and application of digital imaging technology. Advancements in technology, notably the availability of less expensive, high-density memory chips and the development of high speed analog-to-digital converters, mass storage and high performance central processing units have fostered this revolution. Today, most modern SEM instruments have digital electronics as a standard feature. These instruments, generally have 8 bit or 256 gray levels with, at least, 512 × 512 pixel density operating at TV rate. In addition, current slow-scan commercial frame-grabber cards, directly applicable to the SEM, can have upwards of 12-14 bit lateral resolution permitting image acquisition at 4096 × 4096 resolution or greater. The two major categories of SEM systems to which digital technology have been applied are:In the analog SEM system the scan generator is normally operated in an analog manner and the image is displayed in an analog or "slow scan" mode.

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