Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

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Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

Journal of Circuits System and Computers ◽

10.1142/s0218126621501061 ◽

2020 ◽

pp. 2150106

Author(s):

Harekrishna Kumar ◽

V. K. Tomar

Keyword(s):

Power Dissipation ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Static Random Access Memory ◽

Access Time ◽

Access Memory ◽

Subthreshold Region ◽

Noise Margin ◽

Static Noise

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

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Design of Low Power Half Select Free 10T Static Random-Access Memory Cell

Journal of Circuits System and Computers ◽

10.1142/s0218126621500730 ◽

2020 ◽

pp. 2150073 ◽

Cited By ~ 1

Author(s):

Ashish Sachdeva ◽

V. K. Tomar

Keyword(s):

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Static Random Access Memory ◽

Access Time ◽

Signal To Noise ◽

Access Memory ◽

Noise Margin ◽

Sram Cell ◽

Power Delay Product

This paper presents a circuit-level technique of designing a low power and half select free 10T Static Random-Access Memory Cell (SRAM). The proposed cell works with single end read operation and differential write operation. The proposed bit-cell is free from half select issue and supports bit interleaving format. The presented 10T cell exhibits 40.75% lower read power consumption in comparison to conventional 6T SRAM cell, attributed to reduction of activity factor during read operation. The loop cutting transistors used in core latch improve write signal-to-noise margin (WSNM) by 14.94% and read decoupled structure improve read signal-to-noise margin (RSNM) by [Formula: see text] as compared to conventional 6T SRAM. In the proposed work, variability analysis of significant design parameters such as read current, stand-by SNM, and read power of the projected 10T SRAM cell is presented and compared with considered topologies. Mean value of hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than the considered D2p11T cell. The proposed 10T cell shows [Formula: see text] and [Formula: see text] narrower read access time and write access time, respectively, as compared to conventional 6T SRAM cell. Read current to bit-line leakage current ratio of the proposed 10T cell has been investigated and is improved by [Formula: see text] as compared to conventional 6T SRAM cell. The write power delay product and read power delay product of the proposed 10T cell are [Formula: see text] and [Formula: see text] lower than conventional 6T SRAM cell. In this work, cadence virtuoso tool with Generic Process Design Kit (GPDK) 45[Formula: see text]nm technology file has been utilized to carry out simulations.

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3D Cross-Point Spin Transfer Torque Magnetic Random Access Memory

SPIN ◽

10.1142/s2010324717400112 ◽

2017 ◽

Vol 07 (03) ◽

pp. 1740011 ◽

Cited By ~ 6

Author(s):

Hongxin Yang ◽

Xiaobin Wang ◽

Xiaojie Hao ◽

Zihui Wang ◽

Roger Malmhall ◽

...

Keyword(s):

High Performance ◽

Low Cost ◽

Random Access ◽

Random Access Memory ◽

Spin Transfer Torque ◽

Spin Transfer ◽

Access Memory ◽

Cross Point ◽

Magnetic Random Access Memory ◽

Operation Speed

We explore a 3D cross-point spin transfer torque magnetic random access memory (STT-MRAM) array based on the integration of a perpendicular magnetic tunneling junction (pMTJ) with a matching two-terminal selector. The integrated two-terminal device provides a unique opportunity for a high density, low cost stackable storage class memory that can achieve a fast operation speed, long data retention, low bit error rate (BER) and high endurance. 55[Formula: see text]nm size pillar shaped pMTJ and selector devices have been fabricated and characterized. The selector is compatible with pMTJ whether it is in the high or low resistance state. The pMTJ can be RESET and SET after the selector turns on. We model the dynamic switching of the coupled pMTJ and selector devices. Our model shows the importance of the optimal matching of pMTJ magnetic properties with selector resistive properties to achieve high performance.

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Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽

10.3390/nano11061401 ◽

2021 ◽

Vol 11 (6) ◽

pp. 1401

Author(s):

Te Jui Yen ◽

Albert Chin ◽

Vladimir Gritsenko

Keyword(s):

High Performance ◽

Conduction Mechanism ◽

Random Access ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Switching Behavior ◽

Access Memory ◽

Current Voltage ◽

Current Voltage Characteristics ◽

Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

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Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽

10.3390/electronics10121454 ◽

2021 ◽

Vol 10 (12) ◽

pp. 1454

Author(s):

Yoshihiro Sugiura ◽

Toru Tanzawa

Keyword(s):

Time Constant ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Memory Access ◽

Access Time ◽

Access Memory ◽

Delay Times ◽

Cell Current ◽

The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

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Progress and Prospects of Spin Transfer Torque Random Access Memory

IEEE Transactions on Magnetics ◽

10.1109/tmag.2012.2198451 ◽

2012 ◽

Vol 48 (11) ◽

pp. 3025-3030 ◽

Cited By ~ 27

Author(s):

E. Chen ◽

D. Apalkov ◽

A. Driskill-Smith ◽

A. Khvalkovskiy ◽

D. Lottis ◽

...

Keyword(s):

Random Access ◽

Random Access Memory ◽

Spin Transfer Torque ◽

Spin Transfer ◽

Access Memory

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Design and Analysis of SRAM Cell using Negative Bit-Line Write Assist Technique and Separate Read Port for High-Speed Applications

Journal of Circuits System and Computers ◽

10.1142/s0218126621502704 ◽

2021 ◽

pp. 2150270

Author(s):

Jitendra Kumar Mishra ◽

Lakshmi Likhitha Mankali ◽

Kavindra Kandpal ◽

Prasanna Kumar Misra ◽

Manish Goswami

Keyword(s):

Power Dissipation ◽

High Speed ◽

Random Access ◽

Random Access Memory ◽

Access Memory ◽

Static Noise Margin ◽

Semiconductor Memory ◽

Noise Margin ◽

Sram Cell ◽

Static Noise

The present day electronic gadgets have semiconductor memory devices to store data. The static random access memory (SRAM) is a volatile memory, often preferred over dynamic random access memory (DRAM) due to higher speed and lower power dissipation. However, at scaling down of technology node, the leakage current in SRAM often increases and degrades its performance. To address this, the voltage scaling is preferred which subsequently affects the stability and delay of SRAM. This paper therefore presents a negative bit-line (NBL) write assist circuit which is used for enhancing the write ability while a separate (isolated) read buffer circuit is used for improving the read stability. In addition to this, the proposed design uses a tail (stack) transistor to decrease the overall static power dissipation and also to maintain the hold stability. The comparison of the proposed design has been done with state-of-the-art work in terms of write static noise margin (WSNM), write delay, read static noise margin (RSNM) and other parameters. It has been observed that there is an improvement of 48%, 11%, 19% and 32.4% in WSNM while reduction of 33%, 39%, 48% and 22% in write delay as compared to the conventional 6T SRAM cell, NBL, [Formula: see text] collapse and 9T UV SRAM, respectively.

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