New Electronic Interface Circuits for Humidity Measurement Based on the Current Processing Technique

Abstract The paper describes a new electronic conditioning circuit based on the current-processing technique for accurate and reliable humidity measurement, without post-processing requirements. Pseudobrookite nanocrystalline (Fe2TiO5) thick film was used as capacitive humidity transducer in the proposed design. The interface integrated circuit was realized in TSMC 0.18 μm CMOS technology, but commercial devices were used for practical realization. The sensing principle of the sensor was obtained by converting the information on environment humidity into a frequency variable square-wave electric current signal. The proposed solution features high linearity, insensitivity to temperature, as well as low power consumption. The sensor has a linear function with relative humidity in the range of Relative Humidity (RH) 30-90 %, error below 1.5 %, and sensitivity 8.3 x 1014 Hz/F evaluated over the full range of changes. A fast recovery without the need of any refreshing methods was observed with a change in RH. The total power dissipation of readout circuitry was 1 mW.

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Area Efficient Carry Select Adder Using Negative Edge Triggered D-Flipflop

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.573.187 ◽

2014 ◽

Vol 573 ◽

pp. 187-193 ◽

Cited By ~ 1

Author(s):

Anitha Ponnusamy ◽

Palaniappan Ramanathan

Keyword(s):

Integrated Circuit ◽

Power Dissipation ◽

High Speed ◽

Total Power ◽

Single Chip ◽

Flip Flop ◽

Design And Optimization ◽

Negative Edge ◽

Carry Select Adder ◽

Power Delay Product

The recent increase in popularity of portable systems and rapid growth of packaging density in VLSI circuit’s has enable designers to design complex functional units on a single chip. Power, area and speed plays a major role in the design and optimization of an integrated circuit. Carry select adder is high speed final stage adder widely used in many data processing units. In this work, conventional D-flip flop is replaced by a new design using negative edge triggered D-flip flop. The proposed CSA is implemented in a faster partitioned Dadda multiplier and simulated by using MICROWIND tool. The results reveal that for 16 bit CSA improvement of power delay product (PDP) of the proposed design using negative edge triggered D flip flop is 78% & 18% when compared to CSA with BEC and CSA with conventional D flip flop. When CSA implemented in a partitioned Dadda multiplier it results in performance improvement of 74 % with little increase in total power dissipation.

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CMOS implementation of an analogue median filter for image processing in real time

Bulletin of the Polish Academy of Sciences Technical Sciences ◽

10.2478/bpasts-2013-0077 ◽

2013 ◽

Vol 61 (3) ◽

pp. 725-730

Author(s):

W. Jendernalik ◽

J. Jakusz ◽

G. Blakiewicz ◽

S. Szczepański

Keyword(s):

Image Processing ◽

Integrated Circuit ◽

High Speed ◽

Median Filter ◽

Cmos Technology ◽

Vision Chip ◽

Interface Circuits ◽

Photo Sensor ◽

Power Operation ◽

Cmos Implementation

Abstract An analogue median filter, realised in a 0.35 μm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented.

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A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter

10.32920/ryerson.14647467 ◽

2021 ◽

Author(s):

Shahab Ardalan

Keyword(s):

Power Dissipation ◽

Low Voltage ◽

Low Power Design ◽

Cmos Technology ◽

Total Power ◽

Cable Modem ◽

Analog To Digital Converter ◽

Flat Panel Display ◽

Digital Converter ◽

Analog To Digital

A 1.2 V, 8 bit, 100 MSample/Sec Pipeline Analog-to-Digital Converter is designed in 0.18-μm standard CMOS technology. An emphasis was placed on observing the low voltage and low power design. The architecture of this ADC is 1 bit/stage pipelined configuration. With above specifications the designed ADC can be applicable for DVI flat-panel display; Giga bit Ethernet on copper, RGB to LCD converter and cable modem. This designed ADC can achieve SNDR 56dB in 100 MHz sampling frequency with 8 bit resolution. Total power dissipation is 40.6mW and INL is around 1 LSB and the maximum swing of the input is 1 Volt peak to peak which is almost rail-to-rail situation. The core area of the ADC excluding pads is around 0.25mm 2 .

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An integrated circuit to null standby using energy provided by MEMS sensors

ACTA IMEKO ◽

10.21014/acta_imeko.v9i4.741 ◽

2020 ◽

Vol 9 (4) ◽

pp. 144

Author(s):

Roberto La Rosa ◽

A. Y. S. Pandiyan ◽

Carlo Trigona ◽

Bruno Andò ◽

Salvatore Baglio

Keyword(s):

Integrated Circuit ◽

Power Dissipation ◽

Cost Effective ◽

Total Power ◽

Zero Energy ◽

Battery Lifetime ◽

Measurement Systems ◽

Energy Harvesters ◽

Main Target ◽

Smart Measurement

The advent of smart measurement systems and innovative wireless sensor networks evinces the necessity to develop novel solutions for conditioning circuits to be used in autonomous or quasi autonomous measurement systems and sensing nodes. The main problem these systems still face is the question of how to supply the nodes in a cost-effective way, considering that, very often, a battery is required, and consequently, the maintenance labor and cost to replace or recharge it may be high. The main target is to increase battery lifetime by decreasing unnecessary energy consumption as much as possible. In this context, several solutions, including energy harvesters, have already been proposed. One of the main solutions is the reduction of power consumption by the measurement device while in standby, which, in most cases, represents a significant amount of the total power dissipation. To this end, authors have already addressed a zero-energy standby solution able to supply the power requested by the measurement equipment only when the appliance is turned on. In this paper, we present an integrated circuit solution suitable to be used with MEMS scale transducers. The validation and the characterisation of the system will be shown to demonstrate the suitability of the proposed method.

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A 1.2 V, 8-bit, 100 MHz pipelined analog-to-digital converter

10.32920/ryerson.14647467.v1 ◽

2021 ◽

Author(s):

Shahab Ardalan

Keyword(s):

Power Dissipation ◽

Low Voltage ◽

Low Power Design ◽

Cmos Technology ◽

Total Power ◽

Cable Modem ◽

Analog To Digital Converter ◽

Flat Panel Display ◽

Digital Converter ◽

Analog To Digital

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POWER REDUCTION TECHNIQUE USING MULTIPLE SUPPLY VOLTAGE AND SWITCHING ACTIVITY ANALYSIS

Journal of Circuits System and Computers ◽

10.1142/s021812661250079x ◽

2013 ◽

Vol 22 (02) ◽

pp. 1250079

Author(s):

BASHAR HADDAD ◽

AMIN JARRAH

Keyword(s):

Power Dissipation ◽

Supply Voltage ◽

Critical Path ◽

Cmos Technology ◽

Propagation Delay ◽

Activity Analysis ◽

Vlsi Circuits ◽

Total Power ◽

Switching Activity ◽

Activity Factor

Recent demand for low power VLSI circuits has been pushing the development of innovative approaches to reduce power dissipation. Supply voltage (V CC ) and switching activity factor (α) are main sources of dynamic power dissipation in CMOS technology. Furthermore, the power dissipation increases exponentially by the value of supply voltage. New approach based on switching activity analysis and multiple supply voltage is implemented successfully in logical circuits, taking in mind the critical path(s) of the design and switching activity factor of each element in the design. High supply voltage is applied on elements on the critical path(s). Elements off the critical path(s) are classified into categories according to their switching activity factors. The total power dissipation is reduced, while the propagation delay remains without any increase. The proposed approach combines the concepts of critical/non-critical paths and switching activity analysis to assign different V CCs to different elements.

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Approximate arithmetic circuits

International Journal of Reconfigurable and Embedded Systems (IJRES) ◽

10.11591/ijres.v9.i3.pp183-200 ◽

2020 ◽

Vol 9 (3) ◽

pp. 183

Author(s):

Navabharath Reddy G ◽

Sruti Setlam ◽

V. Prakasam ◽

D. Kiran Kumar

Keyword(s):

Low Power ◽

Circuit Design ◽

Integrated Circuit ◽

Power Dissipation ◽

Cmos Technology ◽

Integrated Circuit Design ◽

Compressor Design ◽

Low Power Dissipation ◽

Human Sense ◽

Error Distance

Low power consumption is the necessity for the integrated circuit design in CMOS technology of nanometerscale. Recent research proves that to achieve low power dissipation, implementation of approximate designs is the best design when compared to accurate designs. In most of the multimedia ap- plications, DSP blocks has been used as the core blocks. Most of the video and image processing algorithms implemented by these DSP blocks, where result will be in the form of image or video for human observing. As human sense of observation isless, the output of the DSP blocks allows being numerically approx- imate instead of being accurate. The concession on numerical exactness allows proposing approximate analysis. In this project approximate adders, approximate compressors and multipliers are proposed. Two approximate adders namely PA1 and PA2 are proposed which are of type TGA which provides better results like PA1 comprises of 14 transistors and 2 error distance, achieves reduction in delay by 64.9 % and reduction in power by 74.33% whereas the TGA1 had 16 transistors and more power dissipation.PA2 comprises of 20 transistors and 2 error distance. Similarly PA2 achieves delay reduction by 51.43%, power gets reduced by 67.2%. PDP is reduced by 61.97 % whereas TGA2 had 22 transistors. Approximate 4-2 compressor was proposed in this project to reduce number of partial produt. The compressor design in circuit level took 30 transistors with 4 errors out of 16 combinations whereas existing compressor design 1took 38 and design 2 took 36 transistors. By using the proposed adder and compressors, approximate 4x4 multiplier is proposed. The proposed multiplier achieves delay 124.56 (ns) and power 29.332 (uW)which is reduced by 68.01% in terms of delay and 95.97 % in terms of power when compared to accurate multiplier.

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Implementation of Power Efficient Flash Analogue-to-Digital Converter

Active and Passive Electronic Components ◽

10.1155/2014/723053 ◽

2014 ◽

Vol 2014 ◽

pp. 1-11 ◽

Cited By ~ 3

Author(s):

Taninki Sai Lakshmi ◽

Avireni Srinivasulu ◽

Pittala Chandra Shaker

Keyword(s):

Low Power ◽

Power Dissipation ◽

High Speed ◽

Binary Code ◽

Gray Code ◽

Cmos Technology ◽

Total Power ◽

Digital Converter ◽

Flash Adc ◽

Analogue To Digital

An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC) is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL) to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL) value of −0.30 LSB and differential nonlinearity (DNL) value of −0.24 LSB, of the flash ADC.

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Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

Nanoscience &Nanotechnology-Asia ◽

10.2174/2210681209666190412142207 ◽

2020 ◽

Vol 10 (4) ◽

pp. 534-547

Author(s):

Chiradeep Mukherjee ◽

Saradindu Panda ◽

Asish K. Mukhopadhyay ◽

Bansibadan Maji

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Power Dissipation ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Digital Data ◽

Design Parameters ◽

Flip Flop ◽

Quantum Dot Cellular Automata ◽

Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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