FPGA based co-design of a speed fuzzy logic controller applied to an autonomous car

This paper invests in FPGA technology to control the speed of an autonomous car using fuzzy logic. For that purpose, we propose a co-design based on a novel fuzzy controller IP. It was developed using the hardware language VHDL and driven by the Zynq processor through an SDK software design written in C. The proposed IP acts according to the ambient temperature and the presence or absence of an obstacle and its distance from the car. The partitioning of the co-design tasks divides them into hardware and software parts. The simulation results of the fuzzy IP and those of the complete co-design implementation on a Xilinx Zynq board showed the effectiveness of the proposed controller to meet the target constraints and generate suitable PWM signals. The proposed hardware architecture based on 6-LUT blocks uses 11 times fewer logic resources than other previous similar designs. Also, it can be easily updated when new constraints on the system are to be considered, which makes it suitable for many related applications. Fuzzy computing was accelerated thanks to the use of digital signal processing blocks that ensure parallel processing. Indeed, a complete execution cycle takes only 7 us.

Research on an Improved Three-Level SVPWM Modulation Algorithm Based on ID-NPC Topology

The conventional three-level SVPWM (Space Vector Pulse Width Modulation) algorithm is a basic modulation algorithm, which can be performed easily due to clear modulation ideas. Considering different criteria for sectors, however, the basic vector action time is calculated repeatedly, the selection of vector action sequence is cumbersome, and the algorithm execution time is extended as a result of processing by the digital processing chip. In order to better adapt to the PMSM (Permanent Magnet Synchronous Motor) control requirements of the ID-NPC (Improved Diodes Neutral Point Clamped) topology for converter control objects, the sector judgment part, time effect part and vector synthesis part are optimized according to the principles of saving hardware resources and shortening the execution cycle. The vector synthesis optimization algorithm of 2 × amplitude substitution and the vector synthesis algorithm of 1/2 × amplitude substitution are both proposed. Finally, the ID-NPC topology is used to verify the proposed modulation algorithm.

Development of a Guidance System for Motor Imagery Enhancement Using the Virtual Hand Illusion

Motor imagery (MI) is widely used to produce input signals for brain–computer interfaces (BCI) due to the similarities between MI-BCI and the planning–execution cycle. Despite its usefulness, MI tasks can be ambiguous to users and MI produces weaker cortical signals than motor execution. Existing MI guidance systems, which have been reported to provide visual guidance for MI and enhance MI, still have limitations: insufficient immersion for MI or poor expandability to MI for another body parts. We propose a guidance system for MI enhancement that can immerse users in MI and will be easy to extend to other body parts and target motions with few physical constraints. To make easily extendable MI guidance system, the virtual hand illusion is applied to the MI guidance system with a motion tracking sensor. MI enhancement was evaluated in 11 healthy people by comparison with another guidance system and conventional motor commands for BCI. The results showed that the proposed MI guidance system produced an amplified cortical signal compared to pure MI (p < 0.017), and a similar cortical signal as those produced by both actual execution (p > 0.534) and an MI guidance system with the rubber hand illusion (p > 0.722) in the contralateral region. Therefore, we believe that the proposed MI guidance system with the virtual hand illusion is a viable alternative to existing MI guidance systems in various applications with MI-BCI.

A Design-Task-Oriented Model Assignment Method in Model-Based System Engineering

In model-based system engineering (MBSE), reuse of existing models in the development of a new system can be advantageous. Automatic assignment of existing models to each design task within a design task set has been proven to be feasible. However, while several studies have discussed the significance of models in MBSE and methodologies for models reuse, solving the model reusability problem through a model assignment method has not been discussed. Additionally, a significant challenge in model assignment is to address the conflict between the maximization of the model value summations, which are yielded by assigning the models to a design task set, and the minimization of the execution cycle of the task set. This study (a) proposes a design-task-oriented model assignment method that establishes a multiobjective model, based on a model assignment integration framework, and (b) designs a differential-evolution-combined adaptive nondominated sorting genetic algorithm-II to provide an optimal tradeoff between maximizing the total model values and minimizing the execution cycle of the task set. By comparing the performance of the algorithm in resolving the assignment of models to a design task set with those of two conventional algorithms in a phased-array radar development project, the algorithm’s performance and promotion of system development are verified to be superior. The new method can be applied for developing model scheduling software for MBSE-compliant product development projects to improve using effects of the models and development cycle.

Improving functional density of time-critical applications using hardware-based dynamic reconfiguration and bitstream specialisation

The dynamic reconfiguration of an FPGA has many advantages, but the overhead from the process reduces the functional density of applications. Functional density is an indication of the composite benefits a reconfigured application obtains above its generic counterpart and measures the computational throughput per unit hardware resources. Typically, only quasi-static applications obtain a functional density advantage by dynamically reconfiguring its parameters. Contributing to the functional density reduction of applications with tight time constraints is the overhead to generate a new configuration, and the time it takes to load it onto the device. Normally these applications have to reuse their hardware numerous times between configurations before obtaining a functional density advantage. The most promising reconfiguration method to improve functional density with minimal hardware reuse was one that extracts certain characteristics from the bitstream and then implements a bitstream specialiser that generates new hardware at bit-level while the device is being reconfigured. While it was shown that this method allows reconfiguration of an application in real-time, its effect on functional density was not determined. This paper will show that a significant increase in functional density can be achieved for applications where reconfiguration is required before the next execution cycle of the application.

Resource Allocation Technique for Distributed System using Prioritized Class-Based Algorithm

Distributed Systems (DS) are the systems in which the components are distributed at different locations in a network and these components interact with each other by passing messages. In DS each system has a memory and a processor pair. DS is cost-effective, more reliable and faster when compared to the conventional computer systems. But there are some issues in the allocation of resources in such systems as the resources are shared over a number of systems apart from its own individual tasks. The current literature developed various techniques to allocate the resources efficiently by using basic algorithms based on local and global messages and tradeoffs. However, these methods may not be effective as they require special storage and maintenance and constraints the resource availability. In this paper, an efficient resource allocation technique is developed using prioritization and class-based algorithm. The tasks are first given priority and then resources are allocated by fixing a certain percentage of bandwidth for each priority group per execution cycle. The simulation results show that the proposed algorithm is efficient in resource allocation when compared to the conventional techniques.

Temporal Performance Analysis of Enhanced 8 Bit RISC Architecture

In this paper, we have proposed the development of the Enhanced 8-bit RISC architecture and the temporal performance analysis of the enhanced architecture. The enhanced 8 bit RISC architecture is powered with the additional block called as Co-operative Arithmetic and Logical Unit (CALU). The 8 bit core is designed using FPGA as SPARTAN-6 XC65LX9-3TQG144. The purpose of designing is to integrate number of instructions with additional instructions, which are 16 bits with keeping all original instructions execution having 8 bit format. We have designed the enhanced of 8 bit processor for improvement in speed as well as to speedup of the execution cycle, so that improvement in clock cycles per second for execution of an instruction. The Enhanced RISC architecture is fully compatible with the original core along with old instruction set. The CALU is designed to enhance the multi-byte capabilities of the core. The performance improvement in terms of the clock cycle savings has been recorded. The performance enhancement of average 71% has been recorded by the Enhanced core. The Enhanced RISC core has been developed and simulated on Xilinx Vivado 2017.3.

Improve Manufacturing Execution & Cycle Time through Database LEAN Optimization

Today, all the companies around the world are looking for the best methods and ways to store and ensure the protection of their business information. Semiconductor Manufacturing Industry has huge and quite important daily operation data to store and backup yearly. As we know the storage capabilities increases, this is clear evidence that we are handling more information every day, for this reason is critical that our process to archiving and searching the information needs to be improve it. In this paper that demonstrates the effectiveness of the database script optimization & Lean strategy. Simple changes big impact, waste elimination, improves manufacturing execution and cycle time.