scholarly journals Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates

PLoS ONE ◽  
2021 ◽  
Vol 16 (6) ◽  
pp. e0253289
Author(s):  
Mu Wen Chuan ◽  
Kien Liong Wong ◽  
Munawar Agus Riyadi ◽  
Afiq Hamzah ◽  
Shahrizal Rusli ◽  
...  
Keyword(s):  
Performance Metrics ◽  
Field Effect Transistors ◽  
Ballistic Transport ◽  
Average Power ◽  
Logic Gates ◽  
Propagation Delay ◽  
Digital Logic ◽  
Circuit Performance ◽  
Output Terminal ◽  
Power Delay Product

Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.

Novel Self-Pipelining Approach for Speed-Power Efficient Reliable Binary Multiplication

2020 ◽  
Vol 12 (3) ◽  
pp. 149-158 ◽  
Author(s):  
Aloke Saha ◽  
Rahul Pal ◽  
Jayanta Ghosh
Keyword(s):  
Transient Response ◽  
Power Efficiency ◽  
Average Power ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Power Performance ◽  
Circuit Performance ◽  
Power Efficient ◽  
Power Delay Product ◽  
Pipelined Multiplier

Background: The present study explores a novel self-pipelining strategy that can enhance speed-power efficiency as well as the reliability of a binary multiplier as compared to state-of-art register and wavepipelining. Method: Proper synchronization with efficient clocking between the subsequent self-pipelining stages has been assured to design a self-pipelined multiplier. Each self-pipelining stage consists of self-latching leaf cells that are designed, optimized and evaluated by TSMC 0.18μm CMOS technology with 1.8V supply rail and at 25°C temperature. The T-Spice transient response and simulated results for the designed circuits are presented. The proposed idea has been applied to design 4-b×4-b self-pipelined Wallace- tree multiplier. The multiplier was validated for all possible test patterns and the transient response was evaluated. The circuit performance in terms of propagation delay, average power and Power-Delay- Product (PDP) is recorded. Next, the decomposition logic is applied to design a higher-order multiplier (i.e., 8-bit×8-bit and 16-bit×16-bit) based on the proposed strategy using 4-bit×4-bit self-pipelined multiplier. The designed multiplier was also validated through extensive TSpice simulation for all the required test patterns using W-Edit and the evaluated performance is presented. All the designs, optimizations and evaluations performed are based on BSIM3 device parameter of TSMC 0.18μm CMOS technology with 1.8V supply rail at 25°C temperature using S-Edit of Tanner EDA. Results: The reliability was investigated of the proposed 4-b×4-b multiplier in the temperature range - 40°C to 100°C for maximum PDP variation. Conclusion: A benchmarking analysis in terms of speed-power performance with recent competitive design reveals preeminence of the proposed technique.

Design of ternary subtractor using multiplexers

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tulasi Naga Jyothi Kolanti ◽  
Vasundhara Patel K.S.
Keyword(s):  
Field Effect Transistors ◽  
Process Variations ◽  
Propagation Delay ◽  
Channel Length ◽  
Binary Decision ◽  
Content Type ◽  
The Stability ◽  
Power Delay Product ◽  
Ternary Decision Diagram ◽  
Logic Functions

Purpose The purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors. Design/methodology/approach Conventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs. Findings The performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased. Originality/value The proposed half subtractor and full subtractor show better performance over the existing subtractors.

scholarly journals Design and Performance Analysis of 1-Bit FinFET Full Adder Cells for Subthreshold Region at 16 nm Process Technology

2015 ◽  
Vol 2015 ◽  
pp. 1-13 ◽  
Author(s):  
‘Aqilah binti Abdul Tahrim ◽  
Huei Chaeng Chin ◽  
Cheng Siong Lim ◽  
Michael Loong Peng Tan
Keyword(s):  
High Speed ◽  
Average Power ◽  
Full Adder ◽  
Propagation Delay ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Subthreshold Region ◽  
And Performance ◽  
Power Delay Product ◽  
20 Nm

The scaling process of the conventional 2D-planar metal-oxide semiconductor field-effect transistor (MOSFET) is now approaching its limit as technology has reached below 20 nm process technology. A new nonplanar device architecture called FinFET was invented to overcome the problem by allowing transistors to be scaled down into sub-20 nm region. In this work, the FinFET structure is implemented in 1-bit full adder transistors to investigate its performance and energy efficiency in the subthreshold region for cell designs of Complementary MOS (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission Gate (TG), and Hybrid CMOS (HCMOS). The performance of 1-bit FinFET-based full adder in 16-nm technology is benchmarked against conventional MOSFET-based full adder. The Predictive Technology Model (PTM) and Berkeley Shortchannel IGFET Model-Common Multi-Gate (BSIM-CMG) 16 nm low power libraries are used. Propagation delay, average power dissipation, power-delay-product (PDP), and energy-delay-product (EDP) are analysed based on all four types of full adder cell designs of both FETs. The 1-bit FinFET-based full adder shows a great reduction in all four metric performances. A reduction in propagation delay, PDP, and EDP is evident in the 1-bit FinFET-based full adder of CPL, giving the best overall performance due to its high-speed performance and good current driving capabilities.

scholarly journals PERFORMANCE EVALUTION OF CNTFET-BASED SRAM CELL DESIGN

2014 ◽  
pp. 200-205
Author(s):  
SNEH LATA MUROTIYA ◽  
ARAVIND MATTA ◽  
ANU GUPTA
Keyword(s):  
Low Power ◽  
High Stability ◽  
Ballistic Transport ◽  
Memory Cell ◽  
Cmos Technology ◽  
Superior Performance ◽  
Circuit Performance ◽  
Figures Of Merit ◽  
Sram Cell ◽  
Power Delay Product

Carbon Nanotube Field-Effect Transistor (CNTFET) technology with their excellent current capabilities, ballistic transport operation and superior thermal conductivities has proved to be a very promising and superior alternative to the conventional CMOS technology. A detailed analysis and simulation based assessment of circuit performance of this technology is presented here. As figures of merit speed, power consumption and stability are considered to evaluate the performance parameters of CNTFET-Based SRAM Cells with different chiral vectors for the optimum performance. A novel performance metric, presented as “SPR,” is used to assess these figures of merit. This comprehensive metric includes a metric of low power delay product (PDP) for write operation and high stability in the operation of a memory cell. It is shown that an 8T SRAM cell provides 73% higher SPR than Dual-Chiral based 6T SRAM cell for CNT technology and 124% higher SPR than its CMOS counterpart, thus attaining superior performance. The CNTFET-based 8T SRAM cell demonstrates that it provides high stability, low delay and low power, which is better than CNTFET-based 6T SRAM cell as well as CMOS SRAM cell.

scholarly journals Design and Analysis of CMOS and CNTFET based Ternary Operators for Scrambling

2019 ◽  
Vol 4 (5) ◽  
pp. 575-579
Author(s):  
Gudala Konica . ◽  
Sreenivasulu Mamilla .
Keyword(s):  
Energy Efficient ◽  
Field Effect ◽  
High Performance ◽  
Digital Circuits ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Future Generations ◽  
Power Delay Product

As silicon technology scales down, it is a dominant choice to have high-performance digital circuits. As researchers investigated for high-performance digital circuits for future generations, Carbon Nanotube Field Effect Transistors (CNTFETs) is considered as the most promising technology due to their excellent current driving capability and proved to be an alternative to conventional CMOS technology. A CNTFET based energy efficient ternary operators are proposed for scrambling applications. The transistor-level implementations of operators namely Scrambling Operator1 (SOP1), Scrambling Operator2 (SOP2) and SUM operators are simulated with CMOS and CNTFET in 32 nm technology at 0.9 V supply voltage using Synopsys HSPICE. The performance metrics like Power, Delay and Power-delay product (PDP) are measured and a comparative analysis for CNTFET and CMOS technologies is carried out. The results demonstrate that CNTFET designs have better-optimized results in power, energy consumption, and reduced transistor count.

A ROBUST HIGH-SPEED LOW INPUT IMPEDANCE CMOS CURRENT COMPARATOR

2008 ◽  
Vol 17 (06) ◽  
pp. 1139-1149 ◽  
Author(s):  
VARAKORN KASEMSUWAN ◽  
SURACHET KHUCHAROENSIN
Keyword(s):  
Input Impedance ◽  
High Speed ◽  
Supply Voltage ◽  
Average Power ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Circuit Performance ◽  
Current Comparator ◽  
Low Input ◽  
Voltage Conversion

In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.

scholarly journals Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8203
Author(s):  
Avireni Bhargav ◽  
Phat Huynh
Keyword(s):  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Supply Voltage ◽  
Average Power ◽  
Propagation Delay ◽  
Approximate Computing ◽  
Effect Transistor ◽  
Developing Area ◽  
Power Delay Product

Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power and high performance. In this paper, 10T approximate adder (AA) and 13T approximate adder (AA) designs using carbon nanotube field-effect transistor (CNFET) technology are presented. The simulation for the proposed 10T approximate adder and 13T approximate adder designs were carried out using the HSPICE tool with 32 nm CNFET technology. The metrics, such as average power, power-delay product (PDP), energy delay product (EDP) and propagation delay, were carried out through the HSPICE tool and compared to the existing circuit designs. The supply voltage Vdd provided for the proposed circuit designs was 0.9 V. The results indicated that among the existing full adders and approximate adders found in the review of adders, the proposed circuits consumed less PDP and minimum power with more accuracy.

Detailed Analysis of Ultra Low Power Column Compression WALLACE and DADDA Multiplier in Sub-Threshold Regime

2016 ◽  
pp. 78-123
Author(s):  
Priya Gupta ◽  
Anu Gupta ◽  
Abhijit Asati
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Performance Metrics ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Ultra Low Power ◽  
Ripple Carry Adder ◽  
Power Delay Product ◽  
Threshold Regime

In this chapter, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace and Dadda in sub-threshold regime. In order to reduce the hardware which ultimately reduces area, power and overall power delay product, an energy efficient basic modules of the multipliers like AND gates, half adders, full adders and partial product generate units have been analyzed for sub-threshold operation. At the last stage ripple carry adder is used in both multipliers. The performance metrics considered for the analysis of the multipliers are: power, delay and PDP. Simulation studies are carried out for 8x8-bit and 16x16-bit input data width. The proposed circuits show energy efficient results with Spectre simulations for the TSMC 180nm CMOS technology at 0.4V supply voltage. The proposed multipliers so implemented outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional multipliers.

Improvement of Single-Electron Digital Logic Gates by Utilizing Input Discretizers

2016 ◽  
Vol E99.C (2) ◽  
pp. 285-292 ◽  
Author(s):  
Tran THI THU HUONG ◽  
Hiroshi SHIMADA ◽  
Yoshinao MIZUGAKI
Keyword(s):  
Logic Gates ◽  
Single Electron ◽  
Digital Logic

Nanoscale transistors

2017 ◽  
Author(s):  
Sandip Tiwari
Keyword(s):  
Field Effect Transistors ◽  
Ballistic Transport ◽  
Dimensional Change ◽  
Real Space ◽  
Operational Characteristics ◽  
Statistical Variations ◽  
Channel Transport ◽  
And Control ◽  
Long Channel ◽  
Detailed Nature

This chapter brings together the physical underpinnings of field-effect transistors operating in their nanoscale limits. It tackles the change in dominant behavior from scattering-limited long-channel transport to mesoscopic and few scattering events limits in quantized channels. It looks at electrostatics and a transistor’s controllability as dimensions are shrunk—the interplay of geometry and control—and then brings out the operational characteristics in “off”-state, e.g., the detailed nature of insulator’s implications or threshold voltage’s statistical variations grounded in short-range and long-range effects, and “on”-state, where quantization, quantized channels, ballistic transport and limited scattering are important. It also explores the physical behavior for zero bandgap and monoatomic layer materials by focusing on real-space and reciprocal-space funneling as one of the important dimensional change consequences through a discussion of parasitic resistances.

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