Modifying Buried Layers in Nano-MOSFET for Achieving Reliable Electrical Characteristics

2016 ◽  
Vol 5 (10) ◽  
pp. M113-M117 ◽  
Author(s):  
Meysam Zareiee
2015 ◽  
Vol 76 (1) ◽  
Author(s):  
Chek Yee Ooi ◽  
Lim Soo King

This paper presents a numerical simulation study for electrical characteristics of double-gate (DG) nano-MOSFET at equilibrium thin-body condition. The electrical characteristics which are studied include subband energy (including unprimed and primed subbands), 2D electron density at 77K and 300K ambient temperatures, transmission coefficient, average electron velocity and ballistic current. The ranges of silicon body thickness TSi are 1.0 nm, 1.5 nm and 2.0 nm. The electron transport models used in simulation tool covered quantum model and classical model. Simulation output data are also compared with theoretical discussion.


Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


Author(s):  
A.M. Letsoalo ◽  
M.E. Lee ◽  
E.O. de Neijs

Semiconductor devices require metal contacts for efficient collection of electrical charge. The physics of these metal/semiconductor contacts assumes perfect, abrupt and continuous interfaces between the layers. However, in practice these layers are neither continuous nor abrupt due to poor nucleation conditions and the formation of interfacial layers. The effects of layer thickness, deposition rate and substrate stoichiometry have been previously reported. In this work we will compare the effects of a single deposition technique and multiple depositions on the morphology of indium layers grown on (100) CdTe substrates. The electrical characteristics and specific resistivities of the indium contacts were measured, and their relationships with indium layer morphologies were established.Semi-insulating (100) CdTe samples were cut from Bridgman grown single crystal ingots. The surface of the as-cut slices were mechanically polished using 5μm, 3μm, 1μm and 0,25μm diamond abrasive respectively. This was followed by two minutes immersion in a 5% bromine-methanol solution.


Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.


MRS Advances ◽  
2020 ◽  
Vol 5 (61) ◽  
pp. 3153-3161
Author(s):  
Marco Antonio Juárez Sánchez ◽  
Miguel Ángel Meléndez Lira ◽  
Celestino Odín Rodríguez Nava

AbstractDrug contamination in water is one of the current fields of study. Since 1990, the presence of drugs in drinking water has been a concern to scientists and public. In Mexico, these organic compounds are not efficiently removed in wastewater treatment plants; therefore, alternative methodologies have been studied that allow these compounds to have a high percentage of degradation or be completely degraded. One example of these techniques is heterogeneous photocatalysis which has obtained positive results in the degradation of drugs using ZnO nanoparticles. These are commonly selected for their electrical characteristics, even though they disperse in water and an additional unit operation is required to separate them from the liquid medium. To eliminate drugs with nano particles in a single stage, polycaprolactone-based membranes with adhered ZnO nanoparticles, by means of electrospinning, were prepared to degrade drugs such as diclofenac. The technique used has shown to efficiently break down diclofenac in 4 hours according to the capillary electrophoresis readings.


Author(s):  
Satoshi Taniguchi ◽  
Norihiko Yamaguchi ◽  
Takao Miyajima ◽  
Masao Ikeda

1981 ◽  
Vol 4 ◽  
Author(s):  
T. J. Stultz ◽  
J. F. Gibbons

ABSTRACTStructural and electrical characterization of laser recrystallized LPCVD silicon films on amorphous substrates using a shaped cw laser beam have been performed. In comparing the results to data obtained using a circular beam, it was found that a significant increase in grain size can be achieved and that the surface morphology of the shaped beam recrystallized material was much smoother. It was also found that whereas circular beam recrystallized material has a random grain structure, shaped beam material is highly oriented with a <100> texture. Finally the electrical characteristics of the recrystallized film were very good when measured in directions parallel to the grain boundaries.


2002 ◽  
Vol 716 ◽  
Author(s):  
D. Jacques ◽  
S. Petitdidier ◽  
J.L. Regolini ◽  
K. Barla

AbstractOxide/Nitride dielectric stack is widely used as the standard dielectric for DRAM capacitors. The influence of the chemical cleaning prior to the stack formation has been studied in this work. As a result, morphological data such as stack surface roughness (Atomic Force Microscopy) and silicon nitride (SiN) incubation time for growth are comparable for all the studied cases on <Si>. However, Tof-SIMS exhibits different oxygen content at the Si/stack interface following the different chemical treatments. Electrical measurements show comparable C-V and I-V results, for the same Equivalent Oxide Thickness (same capacitance at strong accumulation i.e.-3V) while the different studied interfaces bring different interface states density with lower values for higher interfacial oxygen content. For DRAM applications, a clear improvement in electrical characteristics is obtained under low interfacial oxygen content conditions. Results are compared in embedded-DRAM cells for which we developed an industrially compatible dielectric deposition sequence to obtain minimum leakage current with maximum specific capacitance and no particular linking constraints.


2019 ◽  
Vol 14 (3) ◽  
pp. 226
Author(s):  
Khanit Matra ◽  
Yottana Tanakaran ◽  
Teerawat Temponsub ◽  
Suphanat Nimbua ◽  
Phanuwat Thab-in ◽  
...  

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