scholarly journals Numerical simulation of Gate shape effect on Self-Heating in nano-MOSFET Transistors with high-k dielectric

2021 ◽  
Author(s):  
Maissa Belkheria ◽  
Fraj Echouchene ◽  
Abdullah Bajahzar ◽  
hafedh belmabrouk
Keyword(s):  
Dielectric Material ◽  
Oxide Thickness ◽  
Shape Effect ◽  
Heating Effect ◽  
The Finite Element Method ◽  
Self Heating ◽  
High K ◽  
High K Dielectric ◽  
Semiconductor Equations ◽  
Nano Mosfet

Abstract The aim of the present work is to investigate numerically the self-heating effect (SHE) in MOSFET transistors based on high-k material taking into account the deformation of the gate under the SHE. The SHE inside the MOSFET transistor is calculated using the electrothermal model based on heat transfer equation coupled with semiconductor equations. The electrothermal model have been solved in 2D-dimension using the finite element method. The high-k dielectric HfO2 have been used as gate oxide. Several gate shapes have been used to analyze their impact on SHE. It is observed that the reduction of equivalent oxide thickness (EOT) reduces the SHE in the MOSFET transistor based in high-k dielectric material. the temperature peak increases quadratically with drain voltage for all MOSFET structures. A decrease in self-heating effect is achieved using the square gate shape.

Analysis of Interface Trap Densities for Al2O3 Dielectric Material Based Ultra Thin MOS Devices

2016 ◽  
Vol 860 ◽  
pp. 25-29 ◽  
Author(s):  
Niladri Pratap Maity ◽  
Rajiv R. Thakur ◽  
Reshmi Maity ◽  
R.K. Thapa ◽  
S. Baishya
Keyword(s):  
Dielectric Material ◽  
Oxide Thickness ◽  
Oxide Semiconductor ◽  
Interface Trap ◽  
Mos Devices ◽  
Novel Approach ◽  
High K ◽  
Conductance Method ◽  
High K Dielectric ◽  
P Type

In this paper the interface trap densities (Dit) are analyzed for ultra thin dielectric material based metal oxide semiconductor (MOS) devices using high-k dielectric material Al2O3. The Dit have been calculated by a novel approach using conductance method and it indicates that by reducing the thickness of the oxide, the Dit increases and similar increase is also found by replacing SiO2 with Al2O3. For the same oxide thickness SiO2 has the lowest Dit and found to be the order of 1011 cm-2eV-1. The Dit is found to be in good agreement with published fabrication results at p-type doping level of 1 × 1017 cm-3. Numerical calculations and solutions are performed by MATLAB and device simulation is done by ATLAS.

scholarly journals Conformal High-K Dielectric Coating of Suspended Single-Walled Carbon Nanotubes by Atomic Layer Deposition

Nanomaterials ◽  
2019 ◽  
Vol 9 (8) ◽  
pp. 1085 ◽  
Author(s):  
Kemelbay ◽  
Tikhonov ◽  
Aloni ◽  
Kuykendall
Keyword(s):  
Carbon Nanotubes ◽  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Atomic Layer ◽  
Oxide Thickness ◽  
Ambient Conditions ◽  
Nucleation Layer ◽  
Layer Deposition ◽  
High K ◽  
High K Dielectric

As one of the highest mobility semiconductor materials, carbon nanotubes (CNTs) have been extensively studied for use in field effect transistors (FETs). To fabricate surround-gate FETs— which offer the best switching performance—deposition of conformal, weakly-interacting dielectric layers is necessary. This is challenging due to the chemically inert surface of CNTs and a lack of nucleation sites—especially for defect-free CNTs. As a result, a technique that enables integration of uniform high-k dielectrics, while preserving the CNT’s exceptional properties is required. In this work, we show a method that enables conformal atomic layer deposition (ALD) of high-k dielectrics on defect-free CNTs. By depositing a thin Ti metal film, followed by oxidation to TiO2 under ambient conditions, a nucleation layer is formed for subsequent ALD deposition of Al2O3. The technique is easy to implement and is VLSI-compatible. We show that the ALD coatings are uniform, continuous and conformal, and Raman spectroscopy reveals that the technique does not induce defects in the CNT. The resulting bilayer TiO2/Al2O3 thin-film shows an improved dielectric constant of 21.7 and an equivalent oxide thickness of 2.7 nm. The electrical properties of back-gated and top-gated devices fabricated using this method are presented.

Multiferroic Bi0.7Dy0.3FeO3 films as high k dielectric material for advanced non-volatile memory devices

2009 ◽  
Vol 45 (16) ◽  
pp. 821 ◽  
Author(s):  
K. Prashanthi ◽  
S.P. Duttagupta ◽  
R. Pinto ◽  
V.R. Palkar
Keyword(s):  
Dielectric Material ◽  
Memory Devices ◽  
High K ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
High K Dielectric

scholarly journals High-K dielectric sulfur-selenium alloys

2019 ◽  
Vol 5 (5) ◽  
pp. eaau9785 ◽  
Author(s):  
Sandhya Susarla ◽  
Thierry Tsafack ◽  
Peter Samora Owuor ◽  
Anand B. Puthirath ◽  
Jordan A. Hachtel ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Metal Oxides ◽  
High Dielectric Constant ◽  
Dielectric Material ◽  
Dielectric Strength ◽  
Dielectric Materials ◽  
High K ◽  
Device Applications ◽  
High K Dielectric ◽  
High Dielectric

Upcoming advancements in flexible technology require mechanically compliant dielectric materials. Current dielectrics have either high dielectric constant, K (e.g., metal oxides) or good flexibility (e.g., polymers). Here, we achieve a golden mean of these properties and obtain a lightweight, viscoelastic, high-K dielectric material by combining two nonpolar, brittle constituents, namely, sulfur (S) and selenium (Se). This S-Se alloy retains polymer-like mechanical flexibility along with a dielectric strength (40 kV/mm) and a high dielectric constant (K = 74 at 1 MHz) similar to those of established metal oxides. Our theoretical model suggests that the principal reason is the strong dipole moment generated due to the unique structural orientation between S and Se atoms. The S-Se alloys can bridge the chasm between mechanically soft and high-K dielectric materials toward several flexible device applications.

Integrated Capacitors with Nb2O5 Dielectric for Decoupling Applications

2009 ◽  
Vol 1158 ◽  
Author(s):  
Susan Jacob ◽  
Leonard W. Schaper ◽  
Mourad Benamara
Keyword(s):  
Photoelectron Spectroscopy ◽  
Dielectric Material ◽  
Niobium Pentoxide ◽  
Maximum Efficiency ◽  
Capacitance Density ◽  
Dielectric Characterization ◽  
Area Efficiency ◽  
High K ◽  
Planar Capacitor ◽  
High K Dielectric

AbstractAs electronic systems are scaling down further and further, there is the constant need to utilize all the board area with maximum efficiency. Since passive components occupy most of the space on boards, it is very important to scale them down. New techniques allow for “integrated” passives as opposed to their discrete counterparts. Integrated capacitors can be embedded within the substrate, leaving room for other components on the board surface. In order to improve the area efficiency of these integrated capacitors, researchers have formed multilayered capacitors in the past. This increases the capacitance density, but is time consuming and expensive due to too many process steps. With increased circuit density, a currently demonstrated dielectric, Ta2O5, could be replaced with a potential high-k dielectric that can store more charge in a smaller area than a capacitor with Ta2O5. Niobium pentoxide (Nb2O5) with k∼41 is an emerging dielectric for high-k capacitor applications. This paper investigates niobium pentoxide as a next generation high-k planar capacitor dielectric. Niobium pentoxide dielectric was formed by reactive sputtering and anodization. Dielectric characterization was done using X-ray photoelectron spectroscopy (XPS), Transmission Electron Microscopy (TEM), and Atomic Force Microscopy (AFM). Thin film planar capacitor structures were fabricated using Nb2O5 dielectric and electrically characterized. The results presented include dielectric material characterization, design, capacitance, and breakdown voltage measurements.

The Influence of Defects and Impurities on Electrical Properties of High-k Dielectrics

2008 ◽  
Vol 608 ◽  
pp. 55-109 ◽  
Author(s):  
Jaroslaw Dąbrowski ◽  
Seiichi Miyazaki ◽  
S. Inumiya ◽  
G. Kozłowski ◽  
G. Lippert ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Carrier Transport ◽  
Dielectric Material ◽  
Electrical Breakdown ◽  
Charge Trapping ◽  
Basic Knowledge ◽  
Dielectric Films ◽  
Low Leakage ◽  
High K ◽  
High K Dielectric

Electrical properties of thin high-k dielectric films are influenced (or even governed) by the presence of macroscopic, microscopic and atomic-size defects. For most applications, a structurally perfect dielectric material with moderate parameters would have sufficiently low leakage and sufficiently long lifetime. But defects open new paths for carrier transport, increasing the currents by orders of magnitude, causing instabilities due to charge trapping, and promoting the formation of defects responsible for electrical breakdown events and for the failure of the film. We discuss how currents flow across the gate stack and how damage is created in the material. We also illustrate the contemporary basic knowledge on hazardous defects (including certain impurities) in high-k dielectrics using the example of a family of materials based on Pr oxides. As an example of the influence of stoichiometry on the electrical pa-rameters of the dielectric, we analyze the effect of nitrogen incorporation into ultrathin Hf silicate films.

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