scholarly journals Increasing Reliability Using Adaptive Cross-Layer Techniques in DRPs: Just-Safe-Enough Responses to Reliability Threats

2020 ◽  
pp. 121-138
Author(s):  
Johannes Maximilian Kühn ◽  
Oliver Bringmann ◽  
Wolfgang Rosenstiel
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Cross Layer ◽  
Carrier Injection ◽  
Semiconductor Technology ◽  
Software Developers ◽  
Dynamically Reconfigurable ◽  
Bias Temperature Instability ◽  
Complexity Cost

AbstractThe developments in the semiconductor industry as predicted by institutions such as the ITRS present a difficult question to hardware and software developers alike: How to implement increasingly complex, power hungry, and critical applications reliably in today’s and tomorrow’s semiconductor technology? The present trend of semiconductor technology is characterized by a sharp increase in complexity, cost, and delicacy. Also, it does not scale along the demands which are still based on and often exceed Moore’s Law. In this chapter, we propose to exploit the architectural redundancies provided by potent, yet energy efficient massively parallel architectures, modeled using Dynamically Reconfigurable Processors (DRP). Using DRPs, we built an extensive cross-layer approach, offering different levels of reliability measures to operating system (OS) and software developers through low-cost hardware redundancy schemes and appropriate physical operating condition tuning. On the hardware side, online testing schemes and error detection are deployed to trigger dynamic remapping to avoid the usage of faulty components. This approach is further complemented through hardware health monitoring that can detect reliability issues such as negative bias temperature instability (NBTI) or hot carrier injection (HCI) before they surface as an error as well as further tuning of operating conditions to delay such phenomena from surfacing.

scholarly journals A Review of the Building Blocks of Silicon Photonics: From Fabrication Perspective

2019 ◽  
Vol 1 (1) ◽  
Author(s):  
Md Jubayer Shawon Shawon ◽  
Feng Li
Keyword(s):  
Full Advantage ◽  
Silicon Photonics ◽  
Process Integration ◽  
State Of The Art ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Building Blocks ◽  
Semiconductor Technology ◽  
Electronic Industry ◽  
Current State

Silicon photonics is a disruptive semiconductor technology that taps into the extraordinary properties of light while taking full advantage of the already matured CMOS processes developed in the semiconductor industry. However, just like electronic industry in the 1970s, currently, Silicon Photonics is in its infancy. The fundamental building blocks of silicon photonics such as waveguides, lasers, modulators, etc. are yet to be fully optimized for low-cost-mass-manufacturing. In this paper, the current state-of-the-art related to developing and optimizing these aforementioned key components will be presented. The challenges of process integration regarding Silicon photonics will also be discussed.

Setting an error detection infrastructure with low cost acoustic wave detectors

2012 ◽  
Vol 40 (3) ◽  
pp. 333-343 ◽  
Author(s):  
Gaurang Upasani ◽  
Xavier Vera ◽  
Antonio González
Keyword(s):  
Acoustic Wave ◽  
Error Detection ◽  
Low Cost

scholarly journals Exploiting Existing Comparators for Fine-Grained Low-Cost Error Detection

2014 ◽  
Vol 11 (3) ◽  
pp. 1-24
Author(s):  
Gulay Yalcin ◽  
Oguz Ergin ◽  
Emrah Islek ◽  
Osman Sabri Unsal ◽  
Adrian Cristal
Keyword(s):  
Error Detection ◽  
Low Cost ◽  
Fine Grained

Via Cleaning Technology for Post Etch Residues

2005 ◽  
Vol 103-104 ◽  
pp. 357-360
Author(s):  
B.G. Sharma ◽  
Chris Prindle
Keyword(s):  
Semiconductor Industry ◽  
Dielectric Materials ◽  
Copper Interconnects ◽  
Limiting Factor ◽  
Device Performance ◽  
Semiconductor Technology ◽  
Widespread Acceptance ◽  
Cleaning Technology ◽  
Rc Delay ◽  
Low K

Interconnect RC delay is the limiting factor for device performance in submicron semiconductor technology. Copper and low-k dielectric materials can reduce this delay and have gained widespread acceptance in the semiconductor industry. The presence of copper interconnects provides unprecedented challenges for via cleaning technology and requires the development of novel process chemistries for improved device capability.

scholarly journals Identifying Opportunities for Exploiting Cross-Layer Interactions in Adaptive Wireless Systems

2007 ◽  
Vol 2007 ◽  
pp. 1-11 ◽  
Author(s):  
Troy Weingart ◽  
Douglas C. Sicker ◽  
Dirk Grunwald
Keyword(s):  
Error Detection ◽  
Software Defined Radio ◽  
Forward Error Correction ◽  
Instant Messaging ◽  
Transport Layer ◽  
Cross Layer ◽  
File Transfer ◽  
Data Link ◽  
Frame Size ◽  
Forward Error

The flexibility of cognitive and software-defined radio heralds an opportunity for researchers to reexamine how network protocol layers operate with respect to providing quality of service aware transmission among wireless nodes. This opportunity is enhanced by the continued development of spectrally responsive devices—ones that can detect and respond to changes in the radio frequency environment. Present wireless network protocols define reliability and other performance-related tasks narrowly within layers. For example, the frame size employed on 802.11 can substantially influence the throughput, delay, and jitter experienced by an application, but there is no simple way to adapt this parameter. Furthermore, while the data link layer of 802.11 provides error detection capabilities across a link, it does not specify additional features, such as forward error correction schemes, nor does it provide a means for throttling retransmissions at the transport layer (currently, the data link and transport layer can function counterproductively with respect to reliability). This paper presents an analysis of the interaction of physical, data link, and network layer parameters with respect to throughput, bit error rate, delay, and jitter. The goal of this analysis is to identify opportunities where system designers might exploit cross-layer interactions to improve the performance of Voice over IP (VoIP), instant messaging (IM), and file transfer applications.

Understanding Mold Compound Behavior on Flip Chip QFN Packages

2018 ◽  
Vol 2018 (1) ◽  
pp. 000125-000128
Author(s):  
Ruby Ann M. Camenforte ◽  
Jason Colte ◽  
Richard Sumalinog ◽  
Sylvester Sanchez ◽  
Jaimal Williamson
Keyword(s):  
Thermal Performance ◽  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Gelation Time ◽  
Molding Process ◽  
Design Quality ◽  
Low Resistance ◽  
Die Attach

Abstract Overmolded Flip Chip Quad Flat No-lead (FCQFN) is a low cost flip chip on leadframe package where there is no need for underfill, and is compatible with Pb free or high Pb metallurgy. A robust leadframe design, quality solder joint formation and an excellent molding process are three factors needed to assemble a high performance FCQFN. It combines the best of both wirebonded QFN and wafer chip scale devices. For example, wafer chip scale has low resistance, but inadequate thermal performance (due to absence of thermal pad), whereas wirebonded QFN has good thermal performance (i.e., heat dissipated through conductive die attach material, through the pad and to the board) but higher resistance. Flip chip QFN combines both positive aspects – that is: low resistance and good thermals. One of the common defects for molded packages across the semiconductor industry is the occurrence of mold voiding as this can potentially affect the performance of a device. This paper will discuss how mold voiding is mitigated by understanding the mold compound behavior on flip chip QFN packages. Taking for example the turbulent mold flow observed on flip chip QFN causing mold voids. Mold compound material itself has a great contribution to mold voids, hence defining the correct attributes of the mold compound is critical. Altering the mold compound property to decrease the mold compound rheology is a key factor. This dynamic interaction between mold compound and flip chip QFN package configuration is the basis for a series of design of experiments using a full factorial matrix. Key investigation points are establishing balance in mold compound chemistry allowing flow between bump pitch, as well as the mold compound rheology, where gelation time has to be properly computed to allow flow across the leadframe. Understanding the flow-ability of mold compound for FCQFN, the speed of flow was optimized to check on its impact on mold voids. Mold airflow optimization is also needed to help fill in tighter bump spacing but vacuum-on time needs to be optimized as well.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

Point-of-Care Systems for Rapid DNA Quantification in Oncology

2008 ◽  
Vol 94 (2) ◽  
pp. 216-225 ◽  
Author(s):  
Marco Bianchessi ◽  
Sarah Burgarella ◽  
Marco Cereda
Keyword(s):  
Point Of Care ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Point Of Care Testing ◽  
Lab On Chip ◽  
Diagnostic Assays ◽  
Care Systems ◽  
Point Of Care Systems ◽  
The Common ◽  
On Chip

The development of new powerful applications and the improvement in fabrication techniques are promising an explosive growth in lab-on-chip use in the upcoming future. As the demand reaches significant levels, the semiconductor industry may enter in the field, bringing its capability to produce complex devices in large volumes, high quality and low cost. The lab-on-chip concept, when applied to medicine, leads to the point-of-care concept, where simple, compact and cheap instruments allow diagnostic assays to be performed quickly by untrained personnel directly at the patient's side. In this paper, some practical and economical considerations are made to support the advantages of point-of-care testing. A series of promising technologies developed by STMicroelectronics on lab-on-chips is also presented, mature enough to enter in the common medical practice. The possible use of these techniques for cancer research, diagnosis and treatment are illustrated together with the benefits offered by their implementation in point-of-care testing.

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