A Reliable and Temperature Variation Tolerant 7T SRAM Cell with Single Bitline Configuration for Low Voltage Application

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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Realization of a triple-tail cell with high input resistance for low-voltage application

International Journal of Electronics ◽

10.1080/002072100412975 ◽

2000 ◽

Vol 87 (9) ◽

pp. 1037-1045 ◽

Cited By ~ 2

Author(s):

Fujihiko Matsumoto ◽

Yasuaki Noguchi

Keyword(s):

Low Voltage ◽

Input Resistance ◽

High Input ◽

High Input Resistance ◽

Voltage Application

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Thermoelectrical properties of graphene knife-coated cellulosic fabrics for defect monitoring in Joule-heated textiles

Journal of Industrial Textiles ◽

10.1177/15280837211056986 ◽

2022 ◽

pp. 152808372110569

Author(s):

Tamara Ruiz-Calleja ◽

Rocío Calderón-Villajos ◽

Marilés Bonet-Aracil ◽

Eva Bou-Belda ◽

Jaime Gisbert-Payá ◽

...

Keyword(s):

Thermal Conductivity ◽

Temperature Increase ◽

Low Voltage ◽

Industrial Applications ◽

Protective Equipment ◽

Voltage Application ◽

Useful Life ◽

Coated Fabrics ◽

Conductive Particles

Knife-coating can confer new properties on different textile substrates efficiently by integrating various compounds into the coating paste. Graphene nanoplatelets (GNP) is one of the most used elements for the functionalization of fabrics in recent years, providing electrical and thermal conductivity to fabrics, later used to develop products such as sensors or heated garments. This paper reports thermoelectrically conductive textiles fabrication through knife-coating of cellulosic fabrics with a GNP load from 0.4 to 2 wt% within an acrylic coating paste. The fabric doped with the highest GNP content reaches a temperature increase of 100°C in few seconds. Besides, it is found out that the thermographic images obtained during the electrical voltage application provide maps of irregularities in the dispersion of conductive particles of the coating and defects produced throughout their useful life. Therefore, the application of a low voltage on the coated fabrics allows fast and effective heating by Joule’s effect, whose thermographic images, in turn, can be used as structural maps to check the quality of the GNP doped coating. The temperature values and the heating rate obtained make these fabrics suitable for heating devices, anti-ice and de-ice systems, and protective equipment, which would be of great interest for industrial applications.

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A 10T Cell Design without Half Select Problem for Bit-Interleaving Architecture in 65nm CMOS

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.373-375.1607 ◽

2013 ◽

Vol 373-375 ◽

pp. 1607-1611

Author(s):

Hong Gang Zhou ◽

Shou Biao Tan ◽

Qiang Song ◽

Chun Yu Peng

Keyword(s):

Error Correction ◽

Low Voltage ◽

Cmos Technology ◽

Soft Error ◽

Error Correction Codes ◽

Cell Design ◽

Low Voltage Operation ◽

Sram Cell ◽

Simulation Results ◽

Nanometer Regime

With the scaling of process technologies into the nanometer regime, multiple-bit soft error problem becomes more serious. In order to improve the reliability and yield of SRAM, bit-interleaving architecture which integrated with error correction codes (ECC) is commonly used. However, this leads to the half select problem, which involves two aspects: the half select disturb and the additional power caused by half-selected cells. In this paper, we propose a new 10T cell to allow the bit-interleaving array while completely eliminating the half select problem, thus allowing low-power and low-voltage operation. In addition, the RSNM and WM of our proposed 10T cell are improved by 21% and nearly one times, respectively, as compared to the conventional 6T SRAM cell in SMIC 65nm CMOS technology. We also conduct a comparison with the conventional 6T cell about the leakage simulation results, which show 14% of leakage saving in the proposed 10T cell.

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Buck Converter for Low-Voltage Application

Handbook of Power Management Circuits ◽

10.1201/b19357-3 ◽

2016 ◽

pp. 43-62

Author(s):

Takashi Nabeshima

Keyword(s):

Low Voltage ◽

Buck Converter ◽

Voltage Application

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Comparative analysis of SRAM cell with leakage power reduction approaches

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i2.7.11083 ◽

2018 ◽

Vol 7 (2.7) ◽

pp. 863

Author(s):

Damarla Paradhasaradhi ◽

Kollu Jaya Lakshmi ◽

Yadavalli Harika ◽

Busa Ravi Teja Sai ◽

Golla Jayanth Krishna

Keyword(s):

Low Power ◽

Power Dissipation ◽

Low Voltage ◽

Power Saving ◽

Vital Role ◽

Power Reduction ◽

Leakage Power ◽

Access Time ◽

Chip Area ◽

Sram Cell

In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T SRAM Cell.

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