CMOS technology-based energy efficient artificial neural session key synchronization for securing IoT

2021 ◽  
Vol 95 ◽  
pp. 107369
Author(s):  
Arindam Sarkar ◽  
Mohammad Zubair Khan ◽  
Abdulfattah Noorwali
Keyword(s):  
Energy Efficient ◽  
Cmos Technology ◽  
Session Key ◽  
Artificial Neural

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

2021 ◽  
Author(s):  
Chaudhry Indra Kumar
Keyword(s):  
Energy Transfer ◽  
Energy Efficient ◽  
Linear Energy Transfer ◽  
Mixed Mode ◽  
Biomedical Applications ◽  
Soft Errors ◽  
Cmos Technology ◽  
Radiation Hardness ◽  
Memory Element ◽  
Low Area

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

scholarly journals Design and Analysis of an Approximate Adder with Hybrid Error Reduction

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 471
Author(s):  
Hyoju Seo ◽  
Yoon Seok Yang ◽  
Yongtae Kim
Keyword(s):  
Energy Efficient ◽  
Cmos Technology ◽  
Error Reduction ◽  
The Other ◽  
Reduction Scheme ◽  
Hardware Cost ◽  
Mean Error ◽  
The Mean ◽  
The Cost ◽  
Error Distance

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

ARTIFICIAL NEURAL COMPUTATIONS IN DIGITAL ARRAYS

1998 ◽  
Vol 08 (05n06) ◽  
pp. 525-539
Author(s):  
HOWARD CARD
Keyword(s):  
Computational Models ◽  
Cmos Technology ◽  
Silicon Area ◽  
Processing Elements ◽  
Stochastic Arithmetic ◽  
Digital Vlsi ◽  
Neural Computations ◽  
Artificial Neural ◽  
Pseudorandom Number Generation ◽  
Regular Arrays

In this paper the properties of artificial neural network computations by digital VLSI systems are discussed. We also comment on artificial computational models, learning algorithms, and digital implementations of ANNs in general. The analysis applies to regular arrays or processing elements performing binary integer arithmetic at various bit precisions. Computation rates are limited by power dissipation which is dependent upon required precision and packaging constraints such as pinout. They also depend strongly on the minimum feature size of the CMOS technology. Custom digital implementations with low bit precision are emphasized, because these circuits require less power and silicon area. This may be achieved using stochastic arithmetic, with pseudorandom number generation using cellular automata.

Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA

2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin
Keyword(s):  
Energy Efficient ◽  
Communication Systems ◽  
Average Power ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Hardware Complexity ◽  
Chip Area ◽  
Ldpc Decoder ◽  
Area Efficient

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

scholarly journals An Efficient and Secure Session Key Management Scheme in Wireless Sensor Network

Complexity ◽  
2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Gulzar Mehmood ◽  
Muhammad Sohail Khan ◽  
Abdul Waheed ◽  
Mahdi Zareei ◽  
Muhammad Fayaz ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Wireless Sensor Network ◽  
Sensor Network ◽  
Key Management ◽  
Energy Efficient ◽  
Sensor Nodes ◽  
Wireless Sensor ◽  
Session Key ◽  
Management Scheme ◽  
Key Management Scheme

Wireless Sensor Network (WSN) is a particular network built from small sensor nodes. These sensor nodes have unique features. That is, it can sense and process data in WSN. WSN has tremendous applications in many fields. Despite the significance of WSN, this kind of network faced several issues. The biggest problems rising in WSN are energy consumption and security. Robust security development is needed to cope with WSN applications. For security purposes in WSN, cryptography techniques are very favorable. However, WSN has resource limitations, which is the main problem in applying any security scheme. Hence, if we are using the cryptography scheme in WSN, we must first guarantee that it must be energy-efficient. Thus, we proposed a secure hybrid session key management scheme for WSN. In this scheme, the major steps of public key cryptography are minimized, and much of the operations are based on symmetric key cryptography. This strategy extensively reduces the energy consumption of WSN and ensures optimum security. The proposed scheme is implemented, and their analysis is performed using different parameters with benchmark schemes. We concluded that the proposed scheme is energy-efficient and outperforms the available benchmark schemes. Furthermore, it provides an effective platform for secure key agreements and management in the WSN environment.

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