Energy efficient 1.8 V step down DC/DC Converter in 0.18 μm CMOS technology with optimized silicon area

2011 ◽  
Author(s):  
Prajakta Panse ◽  
T. Laxminidhi
Keyword(s):  
Energy Efficient ◽  
Cmos Technology ◽  
Silicon Area ◽  
Step Down

An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design

2021 ◽  
Author(s):  
Chaudhry Indra Kumar
Keyword(s):  
Energy Transfer ◽  
Energy Efficient ◽  
Linear Energy Transfer ◽  
Mixed Mode ◽  
Biomedical Applications ◽  
Soft Errors ◽  
Cmos Technology ◽  
Radiation Hardness ◽  
Memory Element ◽  
Low Area

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by [Formula: see text]80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160[Formula: see text][Formula: see text]/mg in 32-nm CMOS technology.

scholarly journals Design of area-efficient GHz range current mode frequency synthesizer using standard CMOS technology

2019 ◽  
Vol 70 (4) ◽  
pp. 323-328
Author(s):  
Dan-Dan Zheng ◽  
Yu-Bin Li ◽  
Chang-Qi Wang ◽  
Kai Huang ◽  
Xiao-Peng Yu
Keyword(s):  
Frequency Synthesizer ◽  
Frequency Tuning ◽  
Supply Voltage ◽  
Current Mode ◽  
Cmos Technology ◽  
Mode Frequency ◽  
Loop Filter ◽  
Silicon Area ◽  
Power Efficient ◽  
A Current

Abstract In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

scholarly journals A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications

2019 ◽  
Vol 28 (07) ◽  
pp. 1950110 ◽  
Author(s):  
K. Hayatleh ◽  
S. Zourob ◽  
R. Nagulapalli ◽  
S. Barker ◽  
N. Yassine ◽  
...  
Keyword(s):  
Biomedical Applications ◽  
High Performance ◽  
Impedance Measurement ◽  
Cmos Technology ◽  
Skin Impedance ◽  
Instrumentation Amplifier ◽  
Measurement Circuit ◽  
Silicon Area ◽  
The Impact ◽  
Mode Interference

This paper describes a high-performance impedance measurement circuit for the application of skin impedance measurement in the early detection of skin cancer. A CMRR improvement technique has been adopted for OTAs to reduce the impact of high-frequency common mode interference. A modified three-OTA instrumentation amplifier (IA) has been proposed to help with the impedance measurement. Such systems offer a quick, noninvasive and painless procedure, thus having considerable advantages over the currently used approach, which is based upon the testing of a biopsy sample. The sensor has been implemented in 65[Formula: see text]nm CMOS technology and post-layout simulations confirm the theoretical claims we made and sensor exhibits sensitivity. Circuit consumes 45[Formula: see text]uW from 1.5[Formula: see text]V power supply. The circuit occupies 0.01954[Formula: see text]mm2 silicon area.

scholarly journals Design and Analysis of an Approximate Adder with Hybrid Error Reduction

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 471
Author(s):  
Hyoju Seo ◽  
Yoon Seok Yang ◽  
Yongtae Kim
Keyword(s):  
Energy Efficient ◽  
Cmos Technology ◽  
Error Reduction ◽  
The Other ◽  
Reduction Scheme ◽  
Hardware Cost ◽  
Mean Error ◽  
The Mean ◽  
The Cost ◽  
Error Distance

This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at the cost of extremely low additional power and area overheads. The proposed hybrid error reduction scheme utilizes only two input bits and adjusts the approximate outputs to reduce the error distance, which leads to an overall improvement in accuracy. The proposed design, when implemented in 65-nm CMOS technology, has 3, 2, and 2 times greater energy, power, and area efficiencies, respectively, than conventional accurate adders. In terms of the accuracy, the proposed hybrid error reduction scheme allows that the error rate of the proposed adder decreases to 50% whereas those of the lower-part OR adder and optimized lower-part OR constant adder reach 68% and 85%, respectively. Furthermore, the proposed adder has up to 2.24, 2.24, and 1.16 times better performance with respect to the mean error distance, normalized mean error distance (NMED), and mean relative error distance, respectively, than the other approximate adder considered in this paper. Importantly, because of an excellent design tradeoff among delay, power, energy, and accuracy, the proposed adder is found to be the most competitive approximate adder when jointly analyzed in terms of the hardware cost and computation accuracy. Specifically, our proposed adder achieves 51%, 49%, and 47% reductions of the power-, energy-, and error-delay-product-NMED products, respectively, compared to the other considered approximate adders.

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

scholarly journals A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications

2020 ◽  
Vol 29 (14) ◽  
pp. 2050220
Author(s):  
Rajasekhar Nagulapalli ◽  
Khaled Hayatleh ◽  
Steve Barker
Keyword(s):  
Positive Feedback ◽  
Cmos Technology ◽  
Voltage Gain ◽  
Silicon Area ◽  
Power Efficient ◽  
Enhancement Technique ◽  
Op Amp ◽  
Gain Enhancement ◽  
Pvt Variations ◽  
Boosting Technique

A power-efficient, voltage gain enhancement technique for op-amps has been described. The proposed technique is robust against Process, Voltage and Temperature (PVT) variations. It exploits a positive feedback-based gain enhancement technique without any latch-up issue, as opposed to the previously proposed conductance cancellation techniques. In the proposed technique, four additional transconductance-stages (gm stages) are used to boost the gain of the main gm stage. The additional gm stages do not significantly increase the power dissipation. A prototype was designed in 65[Formula: see text]nm CMOS technology. It results in 81[Formula: see text]dB voltage gain, which is 21[Formula: see text]dB higher than the existing gain-boosting technique. The proposed op-amp works with as low a power supply as 0.8[Formula: see text]V, without compromising the performance, whereas the traditional gain-enhancement techniques start losing gain below a 1.1[Formula: see text]V supply. The circuit draws a total static current of 295[Formula: see text][Formula: see text]A and occupies 5000[Formula: see text][Formula: see text]m2 of silicon area.

scholarly journals Lossless and Low-Power Image Compressor for Wireless Capsule Endoscopy

VLSI Design ◽  
2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Tareq Hasan Khan ◽  
Khan A. Wahid
Keyword(s):  
Low Power ◽  
Compression Ratio ◽  
Low Complexity ◽  
Cmos Technology ◽  
Silicon Area ◽  
Endoscopic Images ◽  
Prediction Scheme ◽  
Image Pixels ◽  
Image Compressor ◽  
Wireless Capsule

We present a lossless and low-complexity image compression algorithm for endoscopic images. The algorithm consists of a static prediction scheme and a combination of golomb-rice and unary encoding. It does not require any buffer memory and is suitable to work with any commercial low-power image sensors that output image pixels in raster-scan fashion. The proposed lossless algorithm has compression ratio of approximately 73% for endoscopic images. Compared to the existing lossless compression standard such as JPEG-LS, the proposed scheme has better compression ratio, lower computational complexity, and lesser memory requirement. The algorithm is implemented in a 0.18 μm CMOS technology and consumes 0.16 mm × 0.16 mm silicon area and 18 μW of power when working at 2 frames per second.

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