Comprehensive physical analysis of bond wire interfaces in power modules

2016 ◽  
Vol 58 ◽  
pp. 58-64 ◽  
Author(s):  
Vladimir N. Popok ◽  
Kristian B. Pedersen ◽  
Peter K. Kristensen ◽  
Kjeld Pedersen
Keyword(s):  
Physical Analysis ◽  
Power Modules ◽  
Bond Wire

scholarly journals Effect of load sequence interaction on bond-wire lifetime due to power cycling

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Zoubir Khatir ◽  
Son-Ha Tran ◽  
Ali Ibrahim ◽  
Richard Lallemand ◽  
Nicolas Degrenne
Keyword(s):  
High Stress ◽  
Bipolar Transistors ◽  
Junction Temperature ◽  
Experimental Investigations ◽  
Power Cycling ◽  
Power Modules ◽  
Bond Wire ◽  
Load Sequence ◽  
The Difference ◽  
Heating Duration

AbstractExperimental investigations on the effects of load sequence on degradations of bond-wire contacts of Insulated Gate Bipolar Transistors power modules are reported in this paper. Both the junction temperature swing ($$\Delta T_{j}$$ Δ T j ) and the heating duration ($$t_{ON}$$ t ON ) are investigated. First, power cycling tests with single conditions (in $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON ), are performed in order to serve as test references. Then, combined power cycling tests with two-level stress conditions have been done sequentially. These tests are carried-out in the two sequences: low stress/high stress (LH) and high stress/low stress (HL) for both $$\Delta T_{j}$$ Δ T j and $$t_{ON}$$ t ON . The tests conducted show that a sequencing in $$\Delta T_{j}$$ Δ T j regardless of the direction “high-low” or “low–high” leads to an acceleration of degradations and so, to shorter lifetimes. This is more pronounced when the difference between the stress levels is large. With regard to the heating duration ($$t_{ON}$$ t ON ), the effect seems insignificant. However, it is necessary to confirm the effect of this last parameter by additional tests.

scholarly journals Localization and Detection of Bond Wire Faults in Multichip IGBT Power Modules

2020 ◽  
Vol 35 (8) ◽  
pp. 7804-7815 ◽  
Author(s):  
Cuili Chen ◽  
Volker Pickert ◽  
Maher Al-Greer ◽  
Chunjiang Jia ◽  
Chong Ng
Keyword(s):  
Power Modules ◽  
Bond Wire

scholarly journals Using of bond-wire resistance as aging indicator of semiconductor power modules

2020 ◽  
Vol 114 ◽  
pp. 113757
Author(s):  
A. Ibrahim ◽  
Z. Khatir ◽  
J.P. Ousten ◽  
R. Lallemand ◽  
N. Degrenne ◽  
...  
Keyword(s):  
Power Modules ◽  
Bond Wire ◽  
Wire Resistance ◽  
Aging Indicator

Separation of Bond-Wire and Solder Layer Failure Modes in IGBT Power Modules

2020 ◽  
Author(s):  
Wenzhao Liu ◽  
Dao Zhou ◽  
Michael Hartmann ◽  
Francesco Iannuzzo ◽  
Frede Blaabjerg
Keyword(s):  
Failure Modes ◽  
Power Modules ◽  
Bond Wire ◽  
Solder Layer

The Novel Dopant Profile Inspection Methodology by FIB

2010 ◽  
Author(s):  
Po Fu Chou ◽  
Li Ming Lu
Keyword(s):  
High Resolution ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Real Sample ◽  
Physical Analysis ◽  
The Novel ◽  
High Contrast ◽  
Dopant Profile ◽  
P Type

Abstract Dopant profile inspection is one of the focused ion beam (FIB) physical analysis applications. This paper presents a technique for characterizing P-V dopant regions in silicon by using a FIB methodology. This technique builds on published work for backside FIB navigation, in which n-well contrast is observed. The paper demonstrates that the technique can distinguish both n- and p-type dopant regions. The capability for imaging real sample dopant regions on current fabricated devices is also demonstrated. SEM DC and FIB DC are complementary methodologies for the inspection of dopants. The advantage of the SEM DC method is high resolution and the advantage of FIB DC methodology is high contrast, especially evident in a deep N-well region.

A Technique for Reliably Preparing Full-Length Metallographic Cross-Sections of Integrated Circuit Bond Wires

2006 ◽  
Author(s):  
Carl Nail
Keyword(s):  
Integrated Circuits ◽  
High Precision ◽  
Cross Sections ◽  
Integrated Circuit ◽  
Radiographic Analysis ◽  
Good Resolution ◽  
Metallographic Preparation ◽  
Bond Wires ◽  
Darkfield Imaging ◽  
Bond Wire

Abstract To overcome the obstacles in preparing high-precision cross-sections of 'blind' bond wires in integrated circuits, this article proposes a different technique that generates reliable, repeatable cross-sections of bond wires across most or all of their lengths, allowing unencumbered and relatively artifact-free analysis of a given bond wire. The basic method for cross-sectioning a 'blind' bond wire involves radiographic analysis of the sample and metallographic preparation of the sample to the plane of interest. This is followed by tracking the exact location of the plane on the original radiograph using a stereomicroscope and finally darkfield imaging in which the wire is clearly visible with good resolution.

The Electrical Characterization and Physical Failure Analysis for Transistor Gate Leakage

2006 ◽  
Author(s):  
Tsung-Te Li ◽  
Chao-Chi Wu ◽  
Jung-Hsiang Chuang ◽  
Jon C. Lee
Keyword(s):  
Failure Analysis ◽  
Electrical Characterization ◽  
Physical Analysis ◽  
Gate Leakage ◽  
Force Microscopy ◽  
Atomic Force ◽  
Transmission Electron ◽  
Voltage Stress ◽  
Leakage Site

Abstract This article describes the electrical and physical analysis of gate leakage in nanometer transistors using conducting atomic force microscopy (C-AFM), nano-probing, transmission electron microscopy (TEM), and chemical decoration on simulated overstressed devices. A failure analysis case study involving a soft single bit failure is detailed. Following the nano-probing analysis, TEM cross sectioning of this failing device was performed. A voltage bias was applied to exaggerate the gate leakage site. Following this deliberate voltage overstress, a solution of boiling 10%wt KOH was used to etch decorate the gate leakage site followed by SEM inspection. Different transistor leakage behaviors can be identified with nano-probing measurements and then compared with simulation data for increased confidence in the failure analysis result. Nano-probing can be used to apply voltage stress on a transistor or a leakage path to worsen the weak point and then observe the leakage site easier.

Failure Analysis Due to Slightly Unetched Hard Mask Using Nano Probe

2013 ◽  
Author(s):  
Jong Hak Lee ◽  
Jong Eun Kim ◽  
Chang Su Park ◽  
Nam Il Kim ◽  
Jang Won Moon ◽  
...  
Keyword(s):  
Leakage Current ◽  
Circuit Simulation ◽  
The State ◽  
Physical Analysis ◽  
Cross Sectional ◽  
Hard Mask ◽  
Current Flows ◽  
Voltage Contrast ◽  
The One ◽  
Zero Voltage

Abstract In this work, a slightly unetched gate hard mask failure was analyzed by nano probing. Although unetched hard mask failures are commonly detected from the cross sectional view with FIB or FIB-TEM and planar view with the voltage contrast, in this case of the very slightly unetched hard mask, it was difficult to find the defects within the failed area by physical analysis methods. FIB is useful due to its function of milling and checking from the one region to another region within the suspected area, but the defect, located under contact was very tiny. So, it could not be detected in the tilted-view of the FIB. However, the state of the failure could be understood from the electrical analysis using a nano probe due to its ability to probe contact nodes across the fail area. Among the transistors in the fail area, one transistor’s characteristics showed higher leakage current and lower ON current than expected. After physical analysis, slightly remained hard mask was detected by TEM. Chemical processing was followed to determine the gate electrode (WSi2) connection to tungsten contact. It was also proven that when gate is floated, more leakage current flows compared to the state that the zero voltage is applied to the gate. This was not verified by circuit simulation due to the floating nodes.

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