scholarly journals A monolithic InP/SOI platform for integrated photonics

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Zhao Yan ◽  
Yu Han ◽  
Liying Lin ◽  
Ying Xue ◽  
Chao Ma ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Cost Effective ◽  
Silicon On Insulator ◽  
Integrated Photonics ◽  
Photonic Integration ◽  
Fully Integrated ◽  
Power Efficient ◽  
Integration Platform ◽  
Si Photonics ◽  
Industry Standard

AbstractThe deployment of photonic integrated circuits (PICs) necessitates an integration platform that is scalable, high-throughput, cost-effective, and power-efficient. Here we present a monolithic InP on SOI platform to synergize the advantages of two mainstream photonic integration platforms: Si photonics and InP photonics. This monolithic InP/SOI platform is realized through the selective growth of both InP sub-micron wires and large dimension InP membranes on industry-standard (001)-oriented silicon-on-insulator (SOI) wafers. The epitaxial InP is in-plane, dislocation-free, site-controlled, intimately positioned with the Si device layer, and placed right on top of the buried oxide layer to form “InP-on-insulator”. These attributes allow for the realization of various photonic functionalities using the epitaxial InP, with efficient light interfacing between the III–V devices and the Si-based waveguides. We exemplify the potential of this InP/SOI platform for integrated photonics through the demonstration of lasers with different cavity designs including subwavelength wires, square cavities, and micro-disks. Our results here mark a critical step forward towards fully-integrated Si-based PICs.

scholarly journals Emerging heterogeneous integrated photonic platforms on silicon

Nanophotonics ◽  
2015 ◽  
Vol 4 (1) ◽  
pp. 143-164 ◽  
Author(s):  
Sasan Fathpour
Keyword(s):  
Integrated Circuits ◽  
Extinction Ratio ◽  
Nonlinear Effects ◽  
Optical Nonlinearity ◽  
Free Carrier ◽  
Silicon On Insulator ◽  
Integrated Photonics ◽  
Silicon Substrates ◽  
Pure Silicon ◽  
Wide Range

AbstractSilicon photonics has been established as a mature and promising technology for optoelectronic integrated circuits, mostly based on the silicon-on-insulator (SOI) waveguide platform. However, not all optical functionalities can be satisfactorily achieved merely based on silicon, in general, and on the SOI platform, in particular. Long-known shortcomings of silicon-based integrated photonics are optical absorption (in the telecommunication wavelengths) and feasibility of electrically-injected lasers (at least at room temperature). More recently, high two-photon and free-carrier absorptions required at high optical intensities for third-order optical nonlinear effects, inherent lack of second-order optical nonlinearity, low extinction ratio of modulators based on the free-carrier plasma effect, and the loss of the buried oxide layer of the SOI waveguides at mid-infrared wavelengths have been recognized as other shortcomings. Accordingly, several novel waveguide platforms have been developing to address these shortcomings of the SOI platform. Most of these emerging platforms are based on heterogeneous integration of other material systems on silicon substrates, and in some cases silicon is integrated on other substrates. Germanium and its binary alloys with silicon, III–V compound semiconductors, silicon nitride, tantalum pentoxide and other high-index dielectric or glass materials, as well as lithium niobate are some of the materials heterogeneously integrated on silicon substrates. The materials are typically integrated by a variety of epitaxial growth, bonding, ion implantation and slicing, etch back, spin-on-glass or other techniques. These wide range of efforts are reviewed here holistically to stress that there is no pure silicon or even group IV photonics per se. Rather, the future of the field of integrated photonics appears to be one of heterogenization, where a variety of different materials and waveguide platforms will be used for different purposes with the common feature of integrating them on a single substrate, most notably silicon.

Multilayered photonic integration on SOI platform using waveguide-based bridge structure

2018 ◽  
Vol 81 (3) ◽  
pp. 30501
Author(s):  
Saikat Majumder ◽  
Rajib Chakraborty
Keyword(s):  
Integrated Circuits ◽  
Vertical Integration ◽  
Photonic Integrated Circuits ◽  
Single Mode ◽  
Silicon On Insulator ◽  
Multimode Interference ◽  
Photonic Integration ◽  
Bridge Structure ◽  
Feature Size ◽  
Multimode Interference Couplers

A waveguide based structure on silicon on insulator platform is proposed for vertical integration in photonic integrated circuits. The structure consists of two multimode interference couplers connected by a single mode (SM) section which can act as a bridge over any other underlying device. Two more SM sections acts as input and output of the first and second multimode couplers respectively. Potential application of this structure is in multilayered photonic links. It is shown that the efficiency of the structure can be improved by making some design modifications. The entire simulation is done using effective-index based matrix method. The feature size chosen are comparable to waveguides fabricated previously so as to fabricate the proposed structure easily.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

An Overview of 300 mm SOI Starting Wafer Quality and Its Yield Detractors

2005 ◽  
Author(s):  
Pei Y. Tsai ◽  
Junedong Lee ◽  
Paul Ronsheim ◽  
Lindsay Burns ◽  
Richard Murphy ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Device Fabrication ◽  
Sampling Plan ◽  
Silicon On Insulator ◽  
Manufacturing Processes ◽  
Circuit Performance ◽  
Characterization Techniques ◽  
Wafer Manufacturing

Abstract A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

scholarly journals In-Plane Monolithic Integration of Scaled III-V Photonic Devices

2021 ◽  
Vol 11 (4) ◽  
pp. 1887
Author(s):  
Markus Scherrer ◽  
Noelia Vico Triviño ◽  
Svenja Mauthe ◽  
Preksha Tiwari ◽  
Heinz Schmid ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Photonic Devices ◽  
Monolithic Integration ◽  
Light Emitters ◽  
Fully Integrated ◽  
Large Lattice ◽  
Hybrid Iii ◽  
Gain Material

It is a long-standing goal to leverage silicon photonics through the combination of a low-cost advanced silicon platform with III-V-based active gain material. The monolithic integration of the III-V material is ultimately desirable for scalable integrated circuits but inherently challenging due to the large lattice and thermal mismatch with Si. Here, we briefly review different approaches to monolithic III-V integration while focusing on discussing the results achieved using an integration technique called template-assisted selective epitaxy (TASE), which provides some unique opportunities compared to existing state-of-the-art approaches. This method relies on the selective replacement of a prepatterned silicon structure with III-V material and thereby achieves the self-aligned in-plane monolithic integration of III-Vs on silicon. In our group, we have realized several embodiments of TASE for different applications; here, we will focus specifically on in-plane integrated photonic structures due to the ease with which these can be coupled to SOI waveguides and the inherent in-plane doping orientation, which is beneficial to waveguide-coupled architectures. In particular, we will discuss light emitters based on hybrid III-V/Si photonic crystal structures and high-speed InGaAs detectors, both covering the entire telecom wavelength spectral range. This opens a new path towards the realization of fully integrated, densely packed, and scalable photonic integrated circuits.

3-D Silicon-on-Insulator Integrated Circuits With NFET and PFET on Separate Layers Using Au/SiO2Hybrid Bonding

2014 ◽  
Vol 61 (8) ◽  
pp. 2886-2892 ◽  
Author(s):  
Masahide Goto ◽  
Kei Hagiwara ◽  
Yoshinori Iguchi ◽  
Hiroshi Ohtake ◽  
Takuya Saraya ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Silicon On Insulator
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