A V-band VCO with on-chip body bias voltage control technique using 40-nm CMOS process

2017 ◽  
Vol 31 (5) ◽  
pp. 514-521
Author(s):  
Qian Zhou ◽  
Yan Han ◽  
Shifeng Zhang ◽  
Xiaoxia Han ◽  
Ray C. C. Cheung ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Voltage Control ◽  
Control Technique ◽  
Cmos Process ◽  
V Band ◽  
On Chip ◽  
Body Bias

Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Hole Mobility ◽  
Micro Electro Mechanical System ◽  
Cmos Process ◽  
Standard Cmos Process ◽  
Ir Sensor ◽  
Cantilever Structure ◽  
Cmos Mems ◽  
On Chip ◽  
Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

scholarly journals A 1.93-pJ/Bit PCI Express Gen4 PHY Transmitter with On-Chip Supply Regulators in 28 nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (1) ◽  
pp. 68
Author(s):  
Woorham Bae ◽  
Sung-Yong Cho ◽  
Deog-Kyoon Jeong
Keyword(s):  
Finite Impulse Response ◽  
Cmos Process ◽  
Pci Express ◽  
Fully Integrated ◽  
Peripheral Component Interconnect ◽  
Low Power Cmos ◽  
On Chip ◽  
Output Driver ◽  
Wide Operating ◽  
28 Nm

This paper presents a fully integrated Peripheral Component Interconnect (PCI) Express (PCIe) Gen4 physical layer (PHY) transmitter. The prototype chip is fabricated in a 28 nm low-power CMOS process, and the active area of the proposed transmitter is 0.23 mm2. To enable voltage scaling across wide operating rates from 2.5 Gb/s to 16 Gb/s, two on-chip supply regulators are included in the transmitter. At the same time, the regulators maintain the output impedance of the transmitter to meet the return loss specification of the PCIe, by including replica segments of the output driver and reference resistance in the regulator loop. A three-tap finite-impulse-response (FIR) equalization is implemented and, therefore, the transmitter provides more than 9.5 dB equalization which is required in the PCIe specification. At 16 Gb/s, the prototype chip achieves energy efficiency of 1.93 pJ/bit including all the interface, bias, and built-in self-test circuits.

$V$ -band $\times 8$ Frequency Multiplier With Optimized Structure and High Spectral Purity Using 65-nm CMOS Process

2017 ◽  
Vol 27 (5) ◽  
pp. 506-508 ◽  
Author(s):  
Jae-Sun Kim ◽  
Hyun-Myung Oh ◽  
Chul Woo Byeon ◽  
Ju Ho Son ◽  
Jeong Ho Lee ◽  
...  
Keyword(s):  
Frequency Multiplier ◽  
Cmos Process ◽  
Spectral Purity ◽  
V Band

High photon detection efficiency single photon avalanche diode in 0.18 μm standard CMOS process

2017 ◽  
Vol 31 (17) ◽  
pp. 1750193 ◽  
Author(s):  
Wei Wang ◽  
Xiaoyuan Bao ◽  
Li Chen ◽  
Ting Chen ◽  
Guanyu Wang ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Bias Voltage ◽  
Detection Efficiency ◽  
Single Photon ◽  
Cmos Process ◽  
Guard Ring ◽  
Reverse Bias Voltage ◽  
Photon Detection ◽  
Standard Cmos Process ◽  
Photon Detection Efficiency

This paper proposed a single photon avalanche diodes (SPADs) designed with 0.18 [Formula: see text] standard CMOS process. One of the major challenges in CMOS SPADs is how to raise the low photon detection efficiency (PDE). In this paper, the device structure and process parameters of the CMOS SPAD are optimized so as to improve PDE properties which have been investigated in detail. The CMOS SPADs are designed in p+/n-well/deep n-well (DNW) structure with the p-sub and the p-well guard ring (GR). The simulation results show that with the p-well GR, the quantum efficiency (QE) is about 80% with the breakdown voltage of 12.7 V, the unit responsivity is as high as 0.38 A/W and the PDE of 51% and 53% is obtained when the excess bias is at 1 V and 2 V, respectively. The dark count rate (DCR) is 6.2 kHz when bias voltage is 14 V. With the p-sub GR, the breakdown voltage is 13 V, the unit responsivity is up to 0.26 A/W, the QE is 58%, the PDE is 33% and 37% at excess bias of 1 V and 2 V, respectively. The DCR is 3.4 kHz at reverse bias voltage of 14 V.

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