The effect of Fe, Cr and Mo on the resistivity of the top silicon layer of buried oxide silicon-on-insulator structures

1992 ◽  
Vol 7 (8) ◽  
pp. 1067-1071 ◽  
Author(s):  
M M S Puga ◽  
R E Hummel ◽  
D E Burk
Keyword(s):  
Silicon Layer ◽  
Silicon On Insulator ◽  
Buried Oxide

Behavior of contact-silicided TFSOI gate structures

1994 ◽  
Vol 52 ◽  
pp. 860-861
Author(s):  
N. David Theodore ◽  
Juergen Foerstner ◽  
Peter Fejes
Keyword(s):  
Semiconductor Device ◽  
Series Resistance ◽  
Field Effect Transistors ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
Continuous Layer ◽  
Buried Oxide ◽  
Device Structures ◽  
Thin Silicon

As semiconductor device dimensions shrink and packing-densities rise, issues of parasitic capacitance and circuit speed become increasingly important. The use of thin-film silicon-on-insulator (TFSOI) substrates for device fabrication is being explored in order to increase switching speeds. One version of TFSOI being explored for device fabrication is SIMOX (Silicon-separation by Implanted OXygen).A buried oxide layer is created by highdose oxygen implantation into silicon wafers followed by annealing to cause coalescence of oxide regions into a continuous layer. A thin silicon layer remains above the buried oxide (~220 nm Si after additional thinning). Device structures can now be fabricated upon this thin silicon layer.Current fabrication of metal-oxidesemiconductor field-effect transistors (MOSFETs) requires formation of a polysilicon/oxide gate between source and drain regions. Contact to the source/drain and gate regions is typically made by use of TiSi2 layers followedby Al(Cu) metal lines. TiSi2 has a relatively low contact resistance and reduces the series resistance of both source/drain as well as gate regions

ChemInform Abstract: Growth of Buried Oxide Layers of Silicon-on-Insulator (SOI) Structures by Thermal Oxidation of the Top Silicon Layer.

ChemInform ◽  
2010 ◽  
Vol 28 (43) ◽  
pp. no-no
Author(s):  
E. SCHROER ◽  
S. HOPFE ◽  
Q. Y. TONG ◽  
U. GOESELE ◽  
W. SKORUPA
Keyword(s):  
Thermal Oxidation ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Oxide Layers ◽  
Buried Oxide

Growth of Buried Oxide Layers of Silicon‐on‐Insulator Structures by Thermal Oxidation of the Top Silicon Layer

1997 ◽  
Vol 144 (6) ◽  
pp. 2205-2210 ◽  
Author(s):  
E. Schroer ◽  
S. Hopfe ◽  
Q. Y. Tong ◽  
U. Gösele ◽  
W. Skorupa
Keyword(s):  
Thermal Oxidation ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Oxide Layers ◽  
Buried Oxide

The Effects of Annealing Temperature on the Characteristics of Buried Oxide Silicon-On-Insulator

1985 ◽  
Vol 53 ◽  
Author(s):  
B.-Y Mao ◽  
P.-H. Chang ◽  
H.W. Lam ◽  
B.W. Shen ◽  
J.A. Keenan
Keyword(s):  
Annealing Temperature ◽  
Silicon Film ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Thermal Donor ◽  
Buried Oxide ◽  
Lower Oxygen ◽  
Higher Temperature ◽  
Soi Substrates ◽  
Post Implantation

ABSTRACTThe effects of post implantation annealing on the properties of buried oxide silicon-on-insulator (SOI) substrates in the temperature range of 1150°C to 1300°C have been studied. Microstructural analyses showed that the crystallinity of the top silicon layer was improved at higher annealing temperature. Lower thermal donor generation at 450°C was observed in SOI annealed at higher temperature. The improvement in microstructure and lower thermal donor generation were correlated to the lower oxygen concentration in the top silicon film.

A Review of Silicon-On-Insulator Formation by Oxygen Ion Implantation

1983 ◽  
Vol 27 ◽  
Author(s):  
Russell F. Pinizzotto
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
High Energy ◽  
Silicon On Insulator ◽  
Epitaxial Silicon ◽  
Crystal Silicon ◽  
Buried Oxide ◽  
Soi Technology

ABSTRACTSilicon-on-Insulator structures will be an important technological advance used in future VLSI, VHSIC and threedimensional integrated circuits. The most mature SOI technology other than silicon-on-sapphire is SIMOX, or Separation by Implanted Oxygen. High energy oxygen ions are implanted into single crystal silicon until a stoichiometric buried silicon dioxide layer is formed. After implantation, the material is annealed at high temperature to remove implantation induced defects. The structure is completed by the growth of a thin epitaxial silicon layer. Devices and complex circuits have been successfully fabricated by several research groups. This paper reviews the development of this buried oxide SOI technology from 1973 to 1983. The five major sections discuss the advantages of SOI, the basics of buried oxide formation, the literature published between 1973 and 1983, key issues that must be solved before large scale implementation takes place and, finally, predictions of future developments.

Analysis of Silicon-On-Insulator Structures Formed By Oxygen Ion Implantation

1985 ◽  
Vol 43 ◽  
pp. 300-301
Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love
Keyword(s):  
Ion Implantation ◽  
Single Crystal ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Dose ◽  
Crystal Silicon ◽  
Oxygen Ion ◽  
Oxygen Ion Implantation

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.

scholarly journals A Flexible PI/Si/SiO2 Piezoresistive Microcantilever for Trace-Level Detection of Aflatoxin B1

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu
Keyword(s):  
Single Crystal ◽  
Aflatoxin B1 ◽  
Single Crystal Silicon ◽  
Silicon Layer ◽  
Wheatstone Bridge ◽  
Silicon On Insulator ◽  
Passivation Layer ◽  
Spring Constant ◽  
Trace Level ◽  
Crystal Silicon

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

Enhancement of Breakdown Voltage in SOI MOSFET Using Buried p-Type Silicon

2021 ◽  
Author(s):  
Deivakani M ◽  
Sumithra M.G ◽  
Anitha P ◽  
Jenopaul P ◽  
Priyesh P. Gandhi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Impact Ionization ◽  
Semiconductor Industry ◽  
Silicon Layer ◽  
Silicon On Insulator ◽  
Physical Models ◽  
Oxide Semiconductor ◽  
Soi Mosfet ◽  
P Type ◽  
Conventional Device

Abstract Semiconductor industry is still looking for the enhancement of breakdown voltage in Silicon on Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Thus, in this paper, heavy n-type doping below the channel is proposed for SOI MOSFET. Simulation of SOI MOSFET is carried out using 2D TCAD physical simulator. In the conventional device, with no p-type doping is used at the bottom silicon layer. While, in proposed device, p-type doping of 1×1018 cm-3 is used. Physical models are used in the simulation to achieve realistic performance. The models are mobility model, impact ionization model and ohmic contact model. Using TCAD simulation, electron/hole current density, impact generation, recombination and breakdown phenomena are analyzed. It is found that the proposed with p-type doping of 1×1018 cm-3 for SOI MOSFET yields high breakdown voltage. In contrast to conventional device, 20% improvement in breakdown voltage is achieved for proposed device.

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