Analysis of Gate-Source Voltage Spike Generated by Miller Capacitance and Common Source Inductance

2021 ◽  
Author(s):  
Qingshou Yang ◽  
Laili Wang ◽  
Zhiyuan Qi ◽  
Zaojun Ma ◽  
Fengtao Yang ◽  
...  
Keyword(s):  
Common Source ◽  
Source Voltage ◽  
Voltage Spike

A Design of High Frequency Clock Generation Circuit

2013 ◽  
Vol 347-350 ◽  
pp. 1492-1496
Author(s):  
Yan Nan Zhai ◽  
Ling Gao ◽  
Yan Kun Tang ◽  
Jing Li ◽  
Shuang Luan
Keyword(s):  
Duty Cycle ◽  
Average Frequency ◽  
Voltage Source ◽  
Common Source ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Clock Signal ◽  
Clock Generation ◽  
Voltage Amplifier ◽  
Source Voltage

A clock generation circuit is proposed based on CMOSFET technology, which is comprised of a reference voltage source, a common source voltage amplifier, voltage controlled oscillator and timing circuit. By which a particular clock is produced, whose duty cycle is less than 50%. It is used 0.5 μ s CMOS process, HSPICE simulation results indicates that the average frequency of clock signal is 2.071MHz, and the average duty cycle is 31.565% .

scholarly journals A Verilog-A model of an undoped symmetric dual-gate MOSFET

2006 ◽  
Vol 4 ◽  
pp. 303-306 ◽  
Author(s):  
O. Cobianu ◽  
O. Soffke ◽  
M. Glesner
Keyword(s):  
Silicon Film ◽  
Drain Current ◽  
Transcendental Equation ◽  
Common Source ◽  
Soi Mosfet ◽  
Novel Device ◽  
Dual Gate ◽  
Static Regime ◽  
Source Voltage

Abstract. We describe a new procedure of solving the electrostatic potentials in the silicon film of an undoped DG SOI MOSFET structure. Starting from a model previously described in the literature by Malobabic et al. (2004), we propose the bisection method for the solution of transcendental equation giving the surface electrostatic potential of the silicon channel, as a function of the gate to source voltage and the voltage along the channel. The above calculated results are used for obtaining the charges and corresponding drain current in the DG MOSFET transistor. The entire model is implemented in Verilog A and can be used inside Cadence for the determination of the static regime of electrical circuits based on undoped symmetric DG SOI MOSFET. As a case study, a simple common-source amplifier built with such a novel device is analyzed, showing the currents and voltages present in the circuit.

Identifying groups of airborne particles by ordination

1994 ◽  
Vol 52 ◽  
pp. 856-857
Author(s):  
M. Shlepr ◽  
C. M. Vicroy
Keyword(s):  
Elemental Analysis ◽  
Energy Dispersive Spectroscopy ◽  
Manufacturing Process ◽  
Spatial Representation ◽  
Airborne Particles ◽  
Common Source ◽  
Data Set ◽  
Microelectronics Industry ◽  
Induced Changes ◽  
Source Materials

The microelectronics industry is heavily tasked with minimizing contaminates at all steps of the manufacturing process. Particles are generated by physical and/or chemical fragmentation from a mothersource. The tools and macrovolumes of chemicals used for processing, the environment surrounding the process, and the circuits themselves are all potential particle sources. A first step in eliminating these contaminants is to identify their source. Elemental analysis of the particles often proves useful toward this goal, and energy dispersive spectroscopy (EDS) is a commonly used technique. However, the large variety of source materials and process induced changes in the particles often make it difficult to discern if the particles are from a common source.Ordination is commonly used in ecology to understand community relationships. This technique usespair-wise measures of similarity. Separation of the data set is based on discrimination functions. Theend product is a spatial representation of the data with the distance between points equaling the degree of dissimilarity.

Elevated Tissue Factor and Tissue Factor Pathway Inhibitor Circulating Levels in Ischaemic Heart Disease Patients

1998 ◽  
Vol 79 (03) ◽  
pp. 495-499 ◽  
Author(s):  
Anna Maria Gori ◽  
Sandra Fedi ◽  
Ludia Chiarugi ◽  
Ignazio Simonetti ◽  
Roberto Piero Dabizzi ◽  
...  
Keyword(s):  
Heart Disease ◽  
Ischaemic Heart Disease ◽  
Tissue Factor ◽  
Plasma Levels ◽  
Tissue Factor Pathway Inhibitor ◽  
Common Source ◽  
Previous Myocardial Infarction ◽  
Control Subjects ◽  
Tissue Factor Pathway ◽  
Circulating Levels

SummarySeveral studies have shown that thrombosis and inflammation play an important role in the pathogenesis of Ischaemic Heart Disease (IHD). In particular, Tissue Factor (TF) is responsible for the thrombogenicity of the atherosclerotic plaque and plays a key role in triggering thrombin generation. The aim of this study was to evaluate the TF/Tissue Factor Pathway Inhibitor (TFPI) system in patients with IHD.We have studied 55 patients with IHD and not on heparin [18 with unstable angina (UA), 24 with effort angina (EA) and 13 with previous myocardial infarction (MI)] and 48 sex- and age-matched healthy volunteers, by measuring plasma levels of TF, TFPI, Prothrombin Fragment 1-2 (F1+2), and Thrombin Antithrombin Complexes (TAT).TF plasma levels in IHD patients (median 215.4 pg/ml; range 72.6 to 834.3 pg/ml) were significantly (p<0.001) higher than those found in control subjects (median 142.5 pg/ml; range 28.0-255.3 pg/ml).Similarly, TFPI plasma levels in IHD patients were significantly higher (median 129.0 ng/ml; range 30.3-316.8 ng/ml; p <0.001) than those found in control subjects (median 60.4 ng/ml; range 20.8-151.3 ng/ml). UA patients showed higher amounts of TF and TFPI plasma levels (TF median 255.6 pg/ml; range 148.8-834.3 pg/ml; TFPI median 137.7 ng/ml; range 38.3-316.8 ng/ml) than patients with EA (TF median 182.0 pg/ml; range 72.6-380.0 pg/ml; TFPI median 115.2 ng/ml; range 47.0-196.8 ng/ml) and MI (TF median 213.9 pg/ml; range 125.0 to 341.9 pg/ml; TFPI median 130.5 ng/ml; range 94.0-207.8 ng/ml). Similar levels of TF and TFPI were found in patients with mono- or bivasal coronary lesions. A positive correlation was observed between TF and TFPI plasma levels (r = 0.57, p <0.001). Excess thrombin formation in patients with IHD was documented by TAT (median 5.2 μg/l; range 1.7-21.0 μg/l) and F1+2 levels (median 1.4 nmol/l; range 0.6 to 6.2 nmol/l) both significantly higher (p <0.001) than those found in control subjects (TAT median 2.3 μg/l; range 1.4-4.2 μg/l; F1+2 median 0.7 nmol/l; range 0.3-1.3 nmol/l).As in other conditions associated with cell-mediated clotting activation (cancer and DIC), also in IHD high levels of circulating TF are present. Endothelial cells and monocytes are the possible common source of TF and TFPI. The blood clotting activation observed in these patients may be related to elevated TF circulating levels not sufficiently inhibited by the elevated TFPI plasma levels present.

Carrier Redistribution Analysis of Gate-Biased SiC Power-MOSFET Using Super-Higher-Order Scanning Nonlinear Dielectric Microscopy

2015 ◽  
Author(s):  
Norimichi Chinone ◽  
Yasuo Cho
Keyword(s):  
Cross Section ◽  
Measurement System ◽  
Higher Order ◽  
Depletion Layer ◽  
Gate Bias ◽  
Power Mosfet ◽  
Nonlinear Dielectric ◽  
Voltage Dependent ◽  
Carrier Redistribution ◽  
Source Voltage

Abstract Gate-bias dependent depletion layer distribution and carrier distributions in cross-section of SiC power MOSFET were measured by newly developed measurement system based on super-higher-order scanning nonlinear dielectric microscope. The results visualized gate-source voltage dependent redistribution of depletion layer and carrier.

Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs

2014 ◽  
Author(s):  
Ian Kearney ◽  
Hank Sung
Keyword(s):  
New Product Development ◽  
Silicon Oxide ◽  
Low Voltage ◽  
Photon Emission ◽  
Electrical Characterization ◽  
Power Mosfets ◽  
Low Leakage ◽  
A Cell ◽  
Thermographic Analysis ◽  
Voltage Spike

Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

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