A Design of High Frequency Clock Generation Circuit

2013 ◽  
Vol 347-350 ◽  
pp. 1492-1496
Author(s):  
Yan Nan Zhai ◽  
Ling Gao ◽  
Yan Kun Tang ◽  
Jing Li ◽  
Shuang Luan
Keyword(s):  
Duty Cycle ◽  
Average Frequency ◽  
Voltage Source ◽  
Common Source ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Clock Signal ◽  
Clock Generation ◽  
Voltage Amplifier ◽  
Source Voltage

A clock generation circuit is proposed based on CMOSFET technology, which is comprised of a reference voltage source, a common source voltage amplifier, voltage controlled oscillator and timing circuit. By which a particular clock is produced, whose duty cycle is less than 50%. It is used 0.5 μ s CMOS process, HSPICE simulation results indicates that the average frequency of clock signal is 2.071MHz, and the average duty cycle is 31.565% .

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

scholarly journals Evaluasi Performa Fuzzy Logic Controller untuk mengatur kecepatan Motor DC Penguatan Terpisah

2020 ◽  
Vol 12 (2) ◽  
pp. 100-110
Author(s):  
Muhammad Aditya Ardiansyah ◽  
Renny Rakhmawati ◽  
Hendik Eko Hadi Suharyanto ◽  
Era Purwanto
Keyword(s):  
Fuzzy Logic ◽  
Steady State ◽  
Duty Cycle ◽  
Fuzzy Logic Controller ◽  
Dc Motor ◽  
Boost Converter ◽  
Voltage Source ◽  
Single Output ◽  
Multiple Input ◽  
State Error

Beragamnya metode yang ditawarkan oleh fuzzy logic kontroller membuat sebagaian orang meneliti mengenai perbedaan metode inferensi yang digunakan oleh fuzzy logic controller. Sejauh ini terdapat tiga metode fuzzy logic kontroller yang telah dikembangkan yaitu Mamdani, Sugono dan Sukamoto. Pada jurnal ini penggunaan fuzzy logic kontroller akan dievaluasi dengan menggunakan motor dc penguat terpisah sebagai beban untuk melakukan pengaturan kecepatan motor dc. Pada paper ini tujuan utamanya adalah dapat mengendalikan kecepatan dari motor DC Penguatan Terpisah dengan mengatur tegangan jangkar dari motor tersebut. DC motor merupakan salah satu jenis motor memiliki banyak aplikasi dan memiliki kemudahan untuk mengatur kecepatan pada motor tersebut. Logika fuzzy yang digunakan pada studi ini adalah inferensi sugeno dimana dengan konfigurasi Multiple Input Single Output (MiSo). Dimana input berupa error dan perubahan error dan output berupa duty cycle dikarenakan yang dikendalikan oleh logika fuzzy adalah Boost Converter selaku controlled voltage source. Target pada jurnal ini adalah dari kecilnya nilai steady – state error dan minimnya osilasi sehingga mampu membuat sistem lebih stabil. Pada studi ini, Hasil pengujian dilakukan dengan menggunakan Simulink by Matlab dengan Hasil pengujian berupa error rata rata sebesar 5.36%.

scholarly journals PENGUATAN TEGANGAN GENERATOR PERMANEN MAGNET DENGAN MENGGUNAKAN KONVERTER AC-AC

2019 ◽  
pp. 164-171
Author(s):  
Jani F. Mandala
Keyword(s):  
Permanent Magnet ◽  
Duty Cycle ◽  
Boost Converter ◽  
Voltage Gain ◽  
Test Results ◽  
External Voltage ◽  
Voltage Amplifier ◽  
Generator Voltage ◽  
Magnetic Generator

Abstract The study aims to create a permanent magnetic generator voltage amplifier by using a AC-ac converter. To stabilize the external voltage, then used the buck-boost converter. The results showed that by regulating the voltage gain  Buck-Boost converter  at  27 volt voltage  as well as regulating the duty cycle between 1 khz to 5 khz,  can be  generated an external 220 volt through the inverter. The test results of the device can supply stably up to a load of 100 watts.    ABSTRAK Penelitian ini bertujuan untuk membuat penguat tegangan generator permanent magnet dengan menggunakan konverter ac-ac. Untuk menstabilkan luaran tegangan, maka digunakan buck-boost converter. Hasil penelitian menunjukkan bahwa dengan mengatur penguatan tegangan buck-boost converter pada tegangan 27 volt serta mengatur duty cycle antara 1 khz s/d 5 khz, dapat dihasilkan luaran 220 volt melalui inverter. Hasil uji coba perangkat dapat menyuplai dengan stabil sampai pada beban 100 watt.  

A Scalable Millimetre-Wave Differential CMOS Cross-Coupled VCO for Automotive Radar Application

2018 ◽  
Vol 27 (10) ◽  
pp. 1850158 ◽  
Author(s):  
Rekha Yadav ◽  
Pawan Kumar Dahiya ◽  
Rajesh Mishra
Keyword(s):  
Phase Noise ◽  
Oxide Semiconductor ◽  
Control Voltage ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Controlled Oscillator ◽  
Automotive Radar ◽  
Millimetre Wave ◽  
The Impact ◽  
Lc Vco

In this paper, a novel method to realize LC Voltage-Controlled-Oscillator (LC-VCO) operating at 76.2–76.7[Formula: see text]GHz frequency band for microwave RFIC component is presented. The model of cross-coupled differential LC-VCO is designed in 45[Formula: see text]nm technology using Complementary Metal Oxide Semiconductor (CMOS) process for Frequency Modulated Carrier Wave (FMCW) automotive radar sensors and RF transceivers application. The impact of VDD, control voltage and temperature variation on frequency shift, phase noise, and output power has been analyzed to optimize the trade-off between frequency, phase noise, and power requirement. The results depict that LC-VCO dissipates 10.45[Formula: see text]mW power at an operating voltage of 1.5[Formula: see text]V. The phase noise has been observed to be [Formula: see text]90[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset at 76[Formula: see text]GHz carrier frequency. The estimated layout area of IC is [Formula: see text]m2. The result shows the edge of the design over existing techniques.

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