Room Temperature Stable Underfill with Novel Latent Catalyst for Wafer Level Flip-Chip Packaging Applications

2006 ◽  
Author(s):  
Yangyang Sun ◽  
C.P. Wong
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Wafer Level ◽  
Flip Chip Packaging

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

Versatility of Fan Out – Simple 2D to Complex 3D

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 000165-000194
Author(s):  
John Hunt
Keyword(s):  
Flip Chip ◽  
Low Cost ◽  
Cellular Phone ◽  
High Density ◽  
Wafer Level ◽  
Mobile Cellular ◽  
Versatile Tool ◽  
Bga Package ◽  
Flip Chip Packaging ◽  
2D And 3D

Many mobile applications strive for the thinnest package possible, and therefore benefit from the high density of basic Fan Out technology. At the same time, Fan Out has evolved from a simple, single die packaging solution into a high-density solution enabling more complex 2D and 3D connectivity. Fan Out first went into volume manufacturing in 2009 with a simple, single die package using eWLB. For the next few years, it was only thought of in this context. Then in 2016, two packages came into production that broke this stereotype. The first was a hybrid, very high-density Fan Out combined with a BGA package called FOCoS for server applications. The second was a 3D PoP structure for mobile cellular phone applications called InFO. With these structures, Fan Out became a more versatile tool, capable of wider applicability. And since then, multiple manufacturers have continued the evolution of Fan Out's capabilities into more and more packaging opportunities. This presentation will illustrate how the integration of a wide variety of packaging technologies, wafer level processing, substrate evolution and Flip Chip packaging have all come together into both simple and complex packages structures. We will further explore the higher levels of integration and sophistication available using Fan Out as a basic manufacturing technology, describing the evolving functionality and complexity achieved by combining low cost materials and innovative process flows. By using such combinations of tools and processes, the resulting packages are only limited by our imagination and creativity.

Wafer Level Underfill Processing

2000 ◽  
Author(s):  
Luu Nguyen ◽  
Christopher Quentin ◽  
Phuong Nguyen
Keyword(s):  
Flip Chip ◽  
Process Conditions ◽  
Wafer Level ◽  
New Paradigm ◽  
Assembly Method ◽  
Flip Chip Packaging ◽  
The Subject ◽  
The Individual ◽  
Level Process ◽  
Underfill Material

Abstract Underfill materials play a major role in the reliability of flip chip packages. These adhesives have been the subject of much research and development in the last few years, and much improvement in material performance has been obtained. However, the assembly method still remains unchanged, with the underfill being dispensed at the individual die level after flip chip reflow. Even with the arrival of “no-flow” underfills, assembly still requires depositing the underfill material onto the flip chip site prior to positioning the flip chip die. Processing underfill at the wafer level brings in a new paradigm shift to the area of flip chip packaging. Precoating the wafer with the underfill will create significant savings in both time and money. The application cycle time of the wafer level process becomes equivalent to a single dispensing operation for all the good dies on the wafer. This paper will present results obtained with screen printing used as the application method for the wafer level process. An experimental underfill was printed onto un-bumped silicon wafers and cured, and the resultant films were analyzed. Process conditions affecting film thickness and surface roughness were evaluated. Preliminary results with bumped wafers are also discussed.

Flip Chip and Wafer Level Packaging - Past, Present and Future

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 000406-000433
Author(s):  
Peter Elenius
Keyword(s):  
High Speed ◽  
Flip Chip ◽  
Signal Propagation ◽  
Future Market ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Chip Technology ◽  
Current Implementation ◽  
Future Challenges ◽  
Flip Chip Packaging

Flip chip packaging was developed nearly 50 years ago by IBM for the purposes of improved reliability and automated semiconductor assembly. For the first 35 years the use of flip chip technology was limited to a few large IDMs and automotive companies. Beginning fifteen years ago, companies providing flip chip bumping services were established. The primary reason for adoption of flip chip in the 1990s was to enable higher I/O count chips and to improve the power and ground distribution through the use of area array interconnects. Beginning in the early 2000s high speed serial links and other I/O with fast edge rates required the use of flip chip interconnects to improve signal propagation. In the future a greater percentage of devices will utilize flip chip interconnects as these chip requirements continue to drive increased demand. Future challenges include the requirements for better power and ground distribution, finer pitch interconnects and higher I/O count devices while protecting the every more fragile inter layer dielectrics (ILDs) present on the device. Wafer Level Package (WLP) technology was developed approximately fifteen years ago to address form factor requirements in mobile products. Today WLPs play an ever increasing role in both mobile and other applications. An understanding of the market drivers, technology limitations, and variety of WLP structures used will be reviewed from both a historical perspective and current implementation. The breadth of products that are currently packaged with WLPs will also be reviewed. The principal challenges for WLPs both today and historically has been to provide adequate thermal cycle reliability and drop test capability for ever increasing device sizes and ball counts. Future market requirements for WLP technology will likely require new structures that can be cost effectively produced.

Sign in / Sign up

Export Citation Format

Share Document