Wafer Level Underfill Processing

2000 ◽  
Author(s):  
Luu Nguyen ◽  
Christopher Quentin ◽  
Phuong Nguyen
Keyword(s):  
Flip Chip ◽  
Process Conditions ◽  
Wafer Level ◽  
New Paradigm ◽  
Assembly Method ◽  
Flip Chip Packaging ◽  
The Subject ◽  
The Individual ◽  
Level Process ◽  
Underfill Material

Abstract Underfill materials play a major role in the reliability of flip chip packages. These adhesives have been the subject of much research and development in the last few years, and much improvement in material performance has been obtained. However, the assembly method still remains unchanged, with the underfill being dispensed at the individual die level after flip chip reflow. Even with the arrival of “no-flow” underfills, assembly still requires depositing the underfill material onto the flip chip site prior to positioning the flip chip die. Processing underfill at the wafer level brings in a new paradigm shift to the area of flip chip packaging. Precoating the wafer with the underfill will create significant savings in both time and money. The application cycle time of the wafer level process becomes equivalent to a single dispensing operation for all the good dies on the wafer. This paper will present results obtained with screen printing used as the application method for the wafer level process. An experimental underfill was printed onto un-bumped silicon wafers and cured, and the resultant films were analyzed. Process conditions affecting film thickness and surface roughness were evaluated. Preliminary results with bumped wafers are also discussed.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Package Qualification Envelope for 22FDX® Technology

2019 ◽  
Vol 2019 (1) ◽  
pp. 000169-000175
Author(s):  
Christian Klewer ◽  
Frank Kuechenmeister ◽  
Jens Paul ◽  
Dirk Breuer ◽  
Bjoern Boehme ◽  
...  
Keyword(s):  
Flip Chip ◽  
Silicon On Insulator ◽  
Wafer Level ◽  
Characterization Methods ◽  
Fully Depleted ◽  
Individual Market ◽  
The Individual ◽  
Key Aspects ◽  
Board Level ◽  
Board Level Reliability

Abstract This article describes the methodology used to derive the 22FDX® Fully-Depleted Silicon-On-Insulator (FDSOI) Chip Package Interaction (CPI) qualification envelope. In the first part it is discussed how the individual market segments influence the technology features and offerings, including BEOL stacks and package types. In the following, the criteria used for the selection of BEOL stacks, die and package sizes and the interconnect type for the qualification envelope are summarized and explained. The three CPI qualification stages and related characterization methods are presented. CPI test structures used in the envelope are reported and their placement on the technology qualification vehicles (TQV) is outlined on the basis of flip chip TQV. Finally, the paper presents the passing 22FDX® package and board level reliability results obtained for wire bond, flip chip, as well as wafer level fan-in and fan-out package technologies. Key aspects of the individual qualifications are reported.

Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill

2010 ◽  
Vol 2010 (1) ◽  
pp. 000798-000805 ◽  
Author(s):  
Sangil Lee ◽  
Daniel F. Baldwin
Keyword(s):  
Flip Chip ◽  
Void Nucleation ◽  
Void Formation ◽  
Bubble Nucleation ◽  
Nucleation Theory ◽  
High Yield ◽  
Process Conditions ◽  
Assembly Process ◽  
Fine Pitch ◽  
Underfill Material

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 μm) interconnect applications because it has narrowed the feasible assembly process window for achieving robust interconnect yield. In spite of such challenges, a high yield, nearly void-free assembly process has been achieved in the past research using commercial no-flow underfill material with a high I/O, fine pitch FCIP. The initial void area (approximately 7% ) could cause early failures such solders fatigue cracking or solder bridging in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of underfill void nucleation in the no flow assembly process. Based on the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively. This paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high yield, void-free assembly process leveraging a void formation model based on classical bubble nucleation theory. Indeed, the theoretical models were in good agreement with experimental results.

Reduction of Thermal Stress - Part II: Passivation Thickness Optimization of FLATPV Surface Bump Design

2017 ◽  
Vol 2017 (1) ◽  
pp. 000508-000512
Author(s):  
Raj Sekar Sethu ◽  
Salil Hari Kulkarni ◽  
How Ung Ha ◽  
Kok Heng Soon
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Passivation Layer ◽  
Fracture Rate ◽  
Thickness Optimization ◽  
Wafer Level ◽  
Passivation Layers ◽  
Solder Balls ◽  
Interaction Stress ◽  
Underfill Material

Abstract Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material. The flat passivation design can reduce the chip package interaction for underfill material but it needed to be evaluated numerically for wafer level stress before being touted as a solution towards reducing passivation cracks. In Part II of this series of papers, the flat passivation layer thicknesses were numerically simulated and modified using response surface methodology design of experiments (RSM DOE) techniques. The optimized passivation layer thickness showed decreased stress which was validated using a simulation confirmation run.

Ultra-thin Flip-Chip Assembly for Heterogenous and Hybrid Integration

2020 ◽  
Vol 2020 (1) ◽  
pp. 000146-000149
Author(s):  
Douglas Hackler ◽  
Edward Prack
Keyword(s):  
Flip Chip ◽  
Silicon On Insulator ◽  
Smart Devices ◽  
Circuit Boards ◽  
Automated Production ◽  
Wide Range ◽  
Flip Chip Packaging ◽  
Number Of Publications ◽  
The Individual ◽  
Silicon Based

Abstract Flip-chip packaging of thin-die, in fact any packaging of thin-die, is one of today’s most significant challenges for die handling. Despite the difficulties presented as the thickness of chips continues to decrease, the wide range of applications they have enabled across multiple industries has led to increasing interest, as evidenced by the growth in the cumulative total number of publications on thin silicon based electronics, including Ultra-Thin Chips (UTCs), thinning of Silicon-on-Insulator, and wafer thinning. Smart devices including labels, loggers, wearables, implantable medical, and IoT are in demand. A key area of difficulty in the packaging of thin chips comes from removing the individual chips from dicing tape due to the adhesive nature of the tape and die cracking and edge chipping characteristic of thin die. As the industry continues to embrace the benefits afforded by thin devices, two trends are being witnessed. Devices continue to grow larger in area and thinner in thickness. American Semiconductor’s automated production process for packaging and assembly of chips ≤35um in thickness will be presented. This includes details regarding needleless die eject, pick tip design for ultra-thin devices, ultra-thin flip-chip interconnects, thin-chip overcoat, process controls, and assembly on flexible circuit boards (FCB).

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