Temporary bonding on the move towards high volume: A status update on cost-of-ownership

2014 ◽  
Author(s):  
Thomas Uhrmann ◽  
Jurgen Burggraf ◽  
Harald Wiesbauer ◽  
Julian Bravin ◽  
Thorsten Matthias ◽  
...  
Keyword(s):  
High Volume ◽  
Cost Of Ownership ◽  
Temporary Bonding

Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001893-001912
Author(s):  
Thomas Uhrmann ◽  
Jürgen Burggraf ◽  
Harald Wiesbauer ◽  
Julian Bravin ◽  
Thorsten Matthias ◽  
...  
Keyword(s):  
Chemical Stability ◽  
High Volume ◽  
Bonding Process ◽  
Thickness Variation ◽  
Total Thickness ◽  
Process Yield ◽  
Cost Of Ownership ◽  
Temporary Bonding ◽  
Total Thickness Variation ◽  
Determining Factor

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.

Driving down CIGS cost of ownership with high volume thermal deposition systems

2010 ◽  
Author(s):  
John Patrin ◽  
Chad Conroy ◽  
Jian-gang Wen ◽  
Doug Brown ◽  
Ken Pfeiffer ◽  
...  
Keyword(s):  
High Volume ◽  
Thermal Deposition ◽  
Cost Of Ownership

Wafer Thinning for Advanced Packaging Applications

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-26
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Scott Kroeger
Keyword(s):  
Low Cost ◽  
High Volume ◽  
Alternative Methods ◽  
Critical Element ◽  
Wafer Level ◽  
Temporary Bonding ◽  
Scale Down ◽  
Advanced Packaging ◽  
Wafer Thinning ◽  
Etch Profile

Driven largely by the growing need for more data, increased functionality, and faster speeds, consumer electronic devices have sparked a revolution in IC design. As it becomes increasingly more expensive and technically challenging to scale down semiconductor devices, Moore's law is yielding to the concept of “More than Moore”, which is driving integrated functionality in smaller and thinner packages. Packaging for 2.5D and 3D has become critical to new products requiring higher performance and increased functionality in a smaller package. The use of a Through Silicon Via (TSV) has been discussed as a method for stacking die to achieve a vertical interconnect. The high costs associated with this technology have limited TSV use to a few applications such as high-bandwidth memory and logic, slowing its adoption within the industry. Lower-cost advanced packaging concepts have been developed and are now in high-volume production. Recently, alternative methods for exploiting the z-direction have turned to variations of Fan-Out Wafer Level Packaging (FOWLP), which do not include TSVs. In many of these concepts there is a need to thin the wafer to remove all of the silicon while being selective and not etching a variety of other films that include oxides, nitrides, and metals. In addition, there can be temporary bonding adhesives and mold compounds encapsulating the chips; these must remain undamaged. Another critical element of a successful process is the ability to control the profile of the silicon etch to provide uniform removal. The single wafer wet etching techniques and advanced process control developed for TSV Reveal are applicable to these structures and provide a low-cost alternative to CMP and Plasma processes. To successfully execute the process, several characteristics must be met: the silicon overburden depth and profile need to be determined, the overburden thinning etch needs a fast sculpting etchant, and the finishing etchant needs to be selective to materials that will be exposed at the completion of the etch. In addition, the tool used to perform this sequence needs to have the correct metrology capability, along with properly chosen etchants. Similarly, it is not sufficient to know the required etch profile, the software must be able to execute a unique etch profile for each wafer. In this fashion, the finishing etch time can be kept to a minimum. This is important, as many of the selective etchants have a slow etch rate, and adhesives used do not always hold up to exposure to the chemistries involved for long periods. This paper discusses the use of wet etch wafer thinning processes for new FOWLP applications.

Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Using Topcoat-Less Resists

2012 ◽  
Vol 25 (1) ◽  
pp. 63-71 ◽  
Author(s):  
Hamid R. Khorram ◽  
Katsushi Nakano ◽  
Natsuko Sagawa ◽  
Tomoharu Fujiwara ◽  
Yasuhiro Iriuchijima ◽  
...  
Keyword(s):  
High Volume ◽  
Yield Enhancement ◽  
Immersion Lithography ◽  
Cost Of Ownership

Challenges of Scalable 2.5D IC Assembly

2015 ◽  
Vol 12 (3) ◽  
pp. 123-128
Author(s):  
Liang Wang ◽  
Charles G. Woychik ◽  
Guilian Gao ◽  
Grant Villavicencio ◽  
Scott McGrath ◽  
...  
Keyword(s):  
High Volume ◽  
Thermal Dissipation ◽  
Electrical Performance ◽  
High Yield ◽  
Design Stage ◽  
Advantages And Disadvantages ◽  
Interconnect Delay ◽  
Temporary Bonding ◽  
Thermocompression Bonding ◽  
Advanced Packaging

Driven by key metrics, including higher computing performance, lower power consumption, smaller form factor, increased bandwidth, and reduced latency (interconnect delay), the semiconductor interconnect technology is transitioning to 2.5D and gaining acceptance in the industry, as an increasing number of products are beginning to enter volume manufacturing. To transition from today's low volumes to high volume manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput), and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process, and integration choices. With these concerns as a backdrop, our article will discuss our approach to optimizing 2.5D assembly for HVM. This article starts with a review of our test vehicle and our overall choices of substrate, interposer, and die dimensions. Three different 2.5D assembly approaches that have been investigated for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. It is our finding that for achieving high yield and reliability, in the design stage of the system detailed considerations must be given to not only the electrical performance and signal integrity but also the thermal and mechanical behavior of the system in operation as well as the entire process history. This article reports our results from critical areas including temporary bonding, thermocompression bonding, mass reflow, thin wafer/die handling, flux, underfill, and molding. This article also presents our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In the last portion of this article, recommendations are made for an optimized assembly process flow.

Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Using Topcoat-Less Resists

2011 ◽  
Vol 24 (2) ◽  
pp. 173-181 ◽  
Author(s):  
Hamid R. Khorram ◽  
Katsushi Nakano ◽  
Natsuko Sagawa ◽  
Tomoharu Fujiwara ◽  
Yasuhiro Iriuchijima ◽  
...  
Keyword(s):  
High Volume ◽  
Yield Enhancement ◽  
Immersion Lithography ◽  
Cost Of Ownership

Assembly and Scaling Challenges for 2.5D IC

2014 ◽  
Vol 2014 (1) ◽  
pp. 000606-000611 ◽  
Author(s):  
Liang Wang ◽  
Charles G. Woychik ◽  
Guilian Gao ◽  
Scott McGrath ◽  
Hong Shen ◽  
...  
Keyword(s):  
High Volume ◽  
Thermal Dissipation ◽  
Test Vehicle ◽  
Advantages And Disadvantages ◽  
Interconnect Delay ◽  
Critical Areas ◽  
Temporary Bonding ◽  
Advanced Packaging ◽  
Computing Performance ◽  
Material Process

2.5D technology is gaining acceptance in the industry and an increasing number of products are beginning to enter volume manufacturing. As with all interconnect technologies, the key metrics driving the transition include higher computing performance, lower power consumption, smaller form factor, increased bandwidth and reduced latency (interconnect delay). In order to transition from today's low volumes to High Volume Manufacturing (HVM), the concerns of warpage control, thermal dissipation, cost (yield and throughput) and overall technology scalability for future generations need to be addressed rapidly. The solutions in these relatively new packaging technologies encompass design/layout, material, process and integration choices. With these concerns as a backdrop, our paper will discuss our approach to optimizing 2.5D assembly for HVM. We will begin with a review of our test vehicle and our overall choices of substrate, interposer and die dimensions. Three different 2.5D assembly approaches that have been investigated at Invensas for warpage control, ease of process, and impact on yield and reliability will be discussed in detail. We will present our results from critical areas including temporary bonding, thermo-compression bonding, mass reflow, thin wafer/die handling, flux, underfill and molding. This paper will present our understanding of the underlying principles governing the technology bottlenecks in advanced packaging and the three flows will be compared with an assessment of their advantages and disadvantages. In addition, we will also provide the results of our cost modeling work. We will finish by making recommendations for an optimized assembly process flow.

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