Temporary Bonding and De-bonding Process for 2.5D/3D Applications

2020 ◽  
Author(s):  
Qin Ren ◽  
Woon Leng Loh ◽  
Siang Kiat Neo ◽  
King-Jien Chui
Keyword(s):  
Bonding Process ◽  
Temporary Bonding ◽  
3D Applications

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001893-001912
Author(s):  
Thomas Uhrmann ◽  
Jürgen Burggraf ◽  
Harald Wiesbauer ◽  
Julian Bravin ◽  
Thorsten Matthias ◽  
...  
Keyword(s):  
Chemical Stability ◽  
High Volume ◽  
Bonding Process ◽  
Thickness Variation ◽  
Total Thickness ◽  
Process Yield ◽  
Cost Of Ownership ◽  
Temporary Bonding ◽  
Total Thickness Variation ◽  
Determining Factor

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.

scholarly journals Transfer of Tactile Sensors Using Stiction Effect Temporary Handling

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1330
Author(s):  
Peng Zhong ◽  
Ke Sun ◽  
Chaoyue Zheng ◽  
Heng Yang ◽  
Xinxin Li
Keyword(s):  
Silicon Nitride ◽  
Flip Chip ◽  
Tactile Sensor ◽  
Bonding Process ◽  
Electrical Performance ◽  
Tactile Sensors ◽  
Release Process ◽  
Flip Chip Bonding ◽  
Process Reliability ◽  
Temporary Bonding

A novel method for transfer of tactile sensors using stiction effect temporary handling (SETH) is presented to simplify the microelectromechanical-system (MEMS)/CMOS integration process, improve the process reliability and electrical performance, and reduce material constriction. The structure of the tactile sensor and the reroute substrate were first manufactured separately. Following the release process, the stiction-contact structures, which are designed to protect the low-stress silicon nitride diaphragm of the tactile sensor and prevent the low-stress silicon nitride diaphragm from moving during the subsequent bonding process, are temporarily bonded to the substrate owing to the stiction effect. After the released tactile sensor is bonded to the reroute substrate by Au–Si eutectic flip-chip bonding, a pulling force perpendicular to the bonded die is applied to break away the temporary supported beam of the tactile sensor, and the tactile sensor is then successfully transferred to the reroute substrate. The size of the transferred tactile sensor is as small as 180 μm × 180 μm × 1.2 μm, and the force area of the tactile sensor is only 120 μm × 120 μm × 1.2 μm. The maximum misalignment of the flip-chip bonding process is approximately 1.5 μm. The tactile sensors are tested from 0 to 17.1 kPa when the power supply is 5 V, resulting in a sensitivity of 0.22 mV/V/kPa, 0.26 mV/V/kPa, 0.27 mV/V/kPa and 0.27 mV/V/kPa, separately. The stress caused by the Au–Si eutectic flip-chip bonding ranges from −5.83 to +5.54 kPa. The temporary bonding strength caused by stiction is calculated to be larger than 7.06 kPa and less than 22.31 kPa. The shear strength of the bonded test structure is approximately 30.74 MPa and the yield of the transferred tactile sensors is as high as 90%.

ZoneBOND Thin Wafer Support Process for Wafer Bonding Applications

2010 ◽  
Vol 7 (3) ◽  
pp. 138-142 ◽  
Author(s):  
Jeremy McCutcheon ◽  
Robert Brown ◽  
JoElle Dachsteiner
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Bonding Process ◽  
Temporary Bonding ◽  
Higher Temperature

The ZoneBOND process has been developed as an alternative temporary bonding process that bonds at an acceptable temperature (usually less than 200°C), survives through higher-temperature processes, and then debonds at room temperature. The technology utilizes standard silicon or glass carriers and current thermoplastic adhesives developed by Brewer Science, Inc.

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