Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding

2012 ◽  
Author(s):  
A. Phommahaxay ◽  
A. Jourdain ◽  
G. Verbinnen ◽  
T. Woitke ◽  
P. Bisson ◽  
...  
Keyword(s):  
Room Temperature ◽  
Bonding Process ◽  
Ic Manufacturing ◽  
Temporary Bonding

ZoneBOND Thin Wafer Support Process for Wafer Bonding Applications

2010 ◽  
Vol 7 (3) ◽  
pp. 138-142 ◽  
Author(s):  
Jeremy McCutcheon ◽  
Robert Brown ◽  
JoElle Dachsteiner
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Bonding Process ◽  
Temporary Bonding ◽  
Higher Temperature

The ZoneBOND process has been developed as an alternative temporary bonding process that bonds at an acceptable temperature (usually less than 200°C), survives through higher-temperature processes, and then debonds at room temperature. The technology utilizes standard silicon or glass carriers and current thermoplastic adhesives developed by Brewer Science, Inc.

Temporary and permanent bonding enables 3D integration of ultrathin wafers

2019 ◽  
Vol 2019 (DPC) ◽  
pp. 001118-001144
Author(s):  
Elisabeth Brandl ◽  
Thomas Uhrmann ◽  
Mariana Pires ◽  
Stefan Jung ◽  
Jürgen Burggraf ◽  
...  
Keyword(s):  
Mechanical Stability ◽  
Bonding Process ◽  
Total Thickness ◽  
Wafer Level ◽  
3D Integration ◽  
Process Flow ◽  
Wafer Thickness ◽  
Temporary Bonding ◽  
Carrier Wafer ◽  
On Chip

Rising demand in memory is just one example how 3D integration is still gaining momentum. Not only the form factor but also performance is improved for several 3D integration applications by reducing the wafer thickness. Two competing process flows using thin wafers are to carry out for 3D integration today. Firstly, two wafers can be bonded face-to-face with subsequent thinning without the need to handle a thin wafer. However, some chip designs require a face-to-back stacking of thin wafers, where temporary bonding becomes an inevitable process step. In this case, the challenge of the temporary bonding process is different to traditional stacking on chip level, where usually the wafers are diced after debonding and then stacked on chip level, which means die thicknesses are typically in the range of 50 μm. The goal of wafer level transfer is a massive reduction of the wafer thickness. Therefore temporary and permanent bonding has to be combined to enable stacking on wafer level with very thin wafers. The first step is temporary bonding of the device wafer with the temporary carrier through an adhesive interlayer, followed by thinning and other backside processes. Afterwards the thinned wafer is permanently bonded to the target wafer before debonding from the carrier wafer. This can be repeated several times to be suitable for example a high bandwidth memory, where several layers of DRAM are stacked on top of each other. Another application is the memory integration on processors, or die segmentation processes. The temporary bonding process flow has to be very well controlled in terms of total thickness variations (TTV) of the intermediate adhesive between device and carrier wafer. The requirements for the temporary bonding adhesive include offering sufficient adhesion between device and carrier wafer for the subsequent processes. The choice of the material class for this study is the Brewer Science dual layer material comprising of a curable layer which offers high mechanical stability to enable low TTV during the thinning process and a release layer for mechanical debond process. The release layer must lead to a successful debond but prevent spontaneous debonding during grinding and other processes. Total thickness variation values of the adhesive will be analyzed in dependence of the adhesive layer thickness as this is a key criterion for a successful implementation at the manufactures. Besides the TTV the mechanical stability during grinding will be evaluated by CSAM to make sure no delamination has happened. For feasibility of the total process flow it is important that the mechanical debonding requires less force compared to the separation of the permanent bonded wafers. Other process parameters such as edge trimming of the device wafer as well as edge removal of the mechanical debond release layer are investigated.

Temporary Bonding Cost Of Ownership: The link between low total thickness variation and chip yield

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001893-001912
Author(s):  
Thomas Uhrmann ◽  
Jürgen Burggraf ◽  
Harald Wiesbauer ◽  
Julian Bravin ◽  
Thorsten Matthias ◽  
...  
Keyword(s):  
Chemical Stability ◽  
High Volume ◽  
Bonding Process ◽  
Thickness Variation ◽  
Total Thickness ◽  
Process Yield ◽  
Cost Of Ownership ◽  
Temporary Bonding ◽  
Total Thickness Variation ◽  
Determining Factor

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D stacked ICs (3Ds-IC). The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld consumer devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. Temporary bonding and debonding comprises several processes for which yield is essential, as costly fully functional device wafers are being processed. The presented temporary bonding process consists of a bi-layer system, a release layer, Dow Corning WL-3001 Bonding Release and an adhesive layer, Dow Corning WL-4030 or WL-4050 Bonding Adhesive, processed on EVG's 850XT universal temporary bonding and debonding platform. Furthermore, this bi-layer spin coated material allows a room temperature bonding-debonding process increase process throughput which translates to low cost of ownership for high volume manufacturing. As such, this bi-layer approach features high chemical stability exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. Besides chemical stability this adhesive system provides also a high thermal stability when exposed to temperatures up to 300 °C. The temporary bonding process yield has a major impact on the overall Cost of Ownership (CoO). On the other hand, throughput of the individual process steps like spin coating, bonding, cure, debonding and cleaning processes is the second determining factor for improved CoO. In this presentation, we will present a study of the total thickness variation (TTV) and the evolution of TTV at different stages of the process. High resolution in-line metrology is an enabling tool to trace the bond integrity and yield throughout backside processing. As TTV is a major determining factor of the overall process yield, understanding its impact over the bonded wafer pair carries major importance. Especially, non-continuity of the edge region, showing an inherent edge bead after coating, and edge die yield will be focus of our contribution. Finally, our experimental results will be transferred into a cost of ownership model, discussing the pros and cons for high volume production.

Properties of room temperature bonded and UV cured temporary bonding adhesive for ultra-thin wafer's handling

2021 ◽  
Author(s):  
Xujun Li ◽  
Qiang Liu ◽  
Deliang Sun ◽  
Zhipeng Li ◽  
Guoping Zhang ◽  
...  
Keyword(s):  
Room Temperature ◽  
Temporary Bonding

Integrated GaAs Diode Technology for Millimeter and Submillimeter-wave Components and Systems

2000 ◽  
Vol 631 ◽  
Author(s):  
Thomas W. Crowe ◽  
Jeffrey L. Hesler ◽  
William L. Bishop ◽  
Willie E. Bowen ◽  
Richard F. Bradley ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Room Temperature ◽  
Flip Chip ◽  
Quartz Substrate ◽  
Submillimeter Wave ◽  
Bonding Process ◽  
Circuit Performance ◽  
Embedding Impedance ◽  
Compact Range ◽  
The Cost

ABSTRACTGaAs Schottky barrier diodes remain a workhorse technology for submillimeter-wave applications including radio astronomy, chemical spectroscopy, atmospheric studies, plasma diagnostics and compact range radar. This is because of the inherent speed of these devices and their ability to operate at room temperature. Although planar (flip-chip and beam-lead) diodes are replacing whisker contacted diodes throughout this frequency range, the handling and placement of such small GaAs chips limits performance and greatly increases component costs. Through the use of a novel wafer bonding process we have fabricated and tested submillimeter-wave components where the GaAs diode is integrated on a quartz substrate along with other circuit elements such as filters, probes and bias lines. This not only eliminates the cost of handling microscopically small chips, but also improves circuit performance. This is because the parasitic capacitance is reduced by the elimination of the GaAs substrate and the electrical embedding impedance seen by the diodes is more precisely controlled. Our wafer bonding process has been demonstrated through the fabrication and testing of a fundamental mixer at 585 GHz (Tmix < 1200K) and a 380 GHz subharmonically pumped mixer (Tmix < 1000K). This paper reviews the wafer bonding process and discusses how it can be used to greatly improve the performance and manufacturability of submillimeter-wave components.

Covalent Silicon Bonding At Room Temperature In Ultrahigh Vacuum

1997 ◽  
Vol 483 ◽  
Author(s):  
Andreas Plöbl ◽  
Heinz Stenzel ◽  
Qin-Yi Tong ◽  
Martin Langenkamp ◽  
Cord Schmidthals ◽  
...  
Keyword(s):  
Heat Treatment ◽  
Room Temperature ◽  
Ultrahigh Vacuum ◽  
Bonding Process ◽  
Ex Situ ◽  
Hydrogen Passivation ◽  
Bulk Silicon ◽  
Chemical Cleaning ◽  
Covalent Bonds ◽  
Subsequent Activation

AbstractOne possibility of a low temperature joining techniques relies on the bonding of atomically clean surfaces. Results on the application of this method to silicon direct bonding are being presented. Clean surfaces for bonding were prepared by ex situ chemical cleaning with ensuing hydrogen passivation and their subsequent activation by thermal desorption of the hydrogen in ultrahigh vacuum (UHV). In UHV at room temperature, the wafers were gently brought into contact to initiate the bonding process. Without any subsequent heat treatment, the adhesive strength thus achieved was equivalent to the cohesion of bulk silicon: covalent bonds join the two crystals.

Temporary Bonding/Debonding of Silicon Substrates Based on Propylene Carbonate

2015 ◽  
Vol 137 (4) ◽  
Author(s):  
Zhiyuan Zhu ◽  
Min Yu ◽  
Lisha Liu ◽  
Yufeng Jin
Keyword(s):  
Shear Strength ◽  
Uv Radiation ◽  
Propylene Carbonate ◽  
Room Temperature ◽  
Silicon Substrates ◽  
Temporary Bonding ◽  
Photo Acid Generator

This paper researches temporary bonding/debonding based on propylene carbonate (PPC). The highest shear strength of 4.1 MPa was achieved when pure PPC was used as bonding adhesive. Room temperature debonding methods were investigated and compared with thermal debonding. Chemical debonding at room temperature was realized for bonding with the pure PPC. Several different chemicals can be used for chemical debonding. A photo acid generator (PAG)-assisted debonding method was demonstrated at room temperature when PAG-loaded PPC (PAG-PPC) was used as bonding adhesive. The ultraviolet (UV) radiation was used to enhance the PAG-assisted debonding.

ZoneBOND™ Thin Wafer Support Process for Wafer Bonding Applications

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001080-001094 ◽  
Author(s):  
Jeremy McCutcheon ◽  
Robert Brown ◽  
JoElle Dachsteiner
Keyword(s):  
Integrated Circuits ◽  
Wafer Bonding ◽  
Integrated Circuit ◽  
Room Temperature ◽  
Adhesive Bonding ◽  
Temperature Stability ◽  
Optoelectronic Device ◽  
Mems Devices ◽  
Thermal Compression ◽  
Temporary Bonding

Wafer-to-wafer bonding is widely used to support both the production of integrated circuits and MEMS devices. Bonding may be accomplished in a variety of ways including anodic, thermal compression, and adhesive bonding. The bond may be either permanent or temporary. Permanent wafer bonding is used to combine two materials together that remain together for the life of the device, for example, in the production of Si/GaAs wafer heterostructures for integration of an optoelectronic device into silicon integrated circuit technology. Temporary bonding is used to support the device wafer during certain processing steps, and then removed once the device wafer is completed. Currently, there are several temporary bonding processes being developed in industry. The leading technology utilizes some form of polymeric material to temporarily fasten or bond a rigid backing material, usually silicon or glass, to the device wafer for processing. The main issues associated with these techniques are temperature stability of the adhesive, removal from the support wafer, and cleaning the adhesive from the device wafer. The ideal process would require bonding at an acceptable temperature (usually less than 200°C), surviving through higher temperature processes, followed by debonding at lower temperature or even room temperature. In this paper, an alternative solution is reported that utilizes current thermoplastic adhesives and silicon support wafers coupled with a patented technology, developed by Brewer Science, Inc. Support wafers are bonded to device wafers at acceptable temperatures, mechanical integrity is maintained through semiconductor or MEMs processing, and the completely processed device wafer is then safely debonded from the support wafer at room temperature.

Washable Coatings for Packaging Processes

2016 ◽  
Vol 2016 (1) ◽  
pp. 000094-000099
Author(s):  
Alex Brewer ◽  
Alex Laymon ◽  
John Moore
Keyword(s):  
Polyvinyl Alcohol ◽  
Thermal Resistance ◽  
Room Temperature ◽  
Solder Bump ◽  
Dielectric Coating ◽  
Cross Linking ◽  
Thermal Compression ◽  
Temporary Bonding ◽  
Heat Activation ◽  
Industry Needs

Abstract Many packaging processes require the protection of components while another application is conducted. This may include a planarizing coat over large topography while a deposition, bonding, or curing step is completed. Washable coatings are materials that protect the substrate during thermal or mechanical activities and are simply washed away using readily available and green products, such as water or detergent. Washable products are not new, an example includes laser washable coatings that remove debris from the heat activation zone (HAZ) during scribe and break processes. In such cases, thermal resistance is desired as high as possible. The chemistry of washable products includes polyvinyl alcohol (PVA) and polyvinylpyrrolidone (PVP) [1]. While these are excellent choices for consumer packaging (e.g. laundry packets, vitamins), they are best used in electronics for room temperature processing due to their cross-linking upon exposure to heat and metals. Alternatively, thermal resistant and washable products (e.g. DaeCoat™ 515) are available that provide protection to ≥300°C without the aid of mechanical tooling [2]. Planarizing coatings over metals can be thick (&gt;300μm) as in cases where solder bump encapsulation is needed during dielectric coating and cure or when another die is thermal compression bonded. This approach has been demonstrated with washable temporary bonding adhesives in protecting C4 bumps while bonding micro-bumped die onto FPGA interposers [3]. Washable adhesives have been created for thermal and vacuum driven processing as EMI/RFI shielding in a PVD tool. Such coatings are applied to porous substrates, affixing die, processing, and removal by water washing [4]. Success in these and related temporary applications depend upon matching the chemistry of the washable coating with the process. Our experience in creating solutions for these and other industry needs will be discussed as well as the criteria for using temporary washable coatings.

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