Architectural tradeoffs in field-programmable-device-based computing systems

2002 ◽  
Author(s):  
P.K. Chan ◽  
M.D.F. Schlag
Keyword(s):  
Computing Systems ◽  
Field Programmable ◽  
Programmable Device

4459694 Field programmable device with circuitry for detecting poor insulation between adjacent word lines

1985 ◽  
Vol 25 (1) ◽  
pp. 205
Author(s):  
Kouji Ueno ◽  
Toshitak Fukushima ◽  
Kazumi Koyama
Keyword(s):  
Field Programmable ◽  
Programmable Device

scholarly journals Implementation of Leakage Power Reduction Techniques in Field Programmable Device

2019 ◽  
Vol 9 (2) ◽  
pp. 5115-5123
Keyword(s):  
Low Power ◽  
Computer Aided Design ◽  
System Level ◽  
Gate Arrays ◽  
Reduction Techniques ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays ◽  
Power And Energy ◽  
Aided Design

This paper provide a summary of low-power technique for field-programmable gate arrays (FPDs). It cover system level propose technique as well as device level propose methods that have besieged present trade devices. In addition to describe present investigate happening circuit level as well as architecture-level create technique. Current studies on power model as well as on low-power computer-aided design (CAD) are also information. At last, it proposes that would allow the use of Field Programmable Device (FPD) equipment in applications where power and energy consumption is critical, such as mobile devices.

Field-Programmable Gate Array

2021 ◽  
pp. 257-270
Author(s):  
Mário Pereira Véstias
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Array ◽  
Field Programmable Gate Arrays ◽  
Software Systems ◽  
Reconfigurable Logic ◽  
Memory Cache ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.

scholarly journals An Interface for a Decentralized 2D Reconfiguration on Xilinx Virtex-FPGAs for Organic Computing

2009 ◽  
Vol 2009 ◽  
pp. 1-11 ◽  
Author(s):  
Christian Schuck ◽  
Bastian Haetzer ◽  
Jü rgen Becker
Keyword(s):  
Adaptive Systems ◽  
Computing System ◽  
Partial Reconfiguration ◽  
Computing Systems ◽  
Gate Arrays ◽  
Specific Performance ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Organic Computing

Partial and dynamic online reconfiguration of Field Programmable Gate Arrays (FPGAs) is a promising approach to design high adaptive systems with lower power consumption, higher task specific performance, and even build-in fault tolerance. Different techniques and tool flows have been successfully developed. One of them, the two-dimensional partial reconfiguration, based on the Readback-Modify-Writeback method implemented on Xilinx Virtex devices, makes them ideally suited to be used as a hardware platform in future organic computing systems, where a highly adaptive hardware is necessary. In turn, decentralisation, the key property of an organic computing system, is in contradiction with the central nature of the FPGAs configuration port. Therefore, this paper presents an approach that connects the single ICAP port to a network on chip (NoC) to provide access for all clients of the network. Through this a virtual decentralisation of the ICAP is achieved. Further true 2-dimensional partial reconfiguration is raised to a higher level of abstraction through a lightweight Readback-Modify-Writeback hardware module with different configuration and addressing modes. Results show that configuration data as well as reconfiguration times could be significantly reduced.

UNIVERSAL PROGRAMMABLE CHAOS GENERATOR: DESIGN AND IMPLEMENTATION ISSUES

2010 ◽  
Vol 20 (02) ◽  
pp. 419-435 ◽  
Author(s):  
RECAI KILIC
Keyword(s):  
Real Time ◽  
Chaotic Systems ◽  
Analog Circuit ◽  
Loop Model ◽  
Analog Device ◽  
Design And Implementation ◽  
Chaos Generator ◽  
Programmable Analog ◽  
Field Programmable ◽  
Programmable Device

Chaos generators are generally designed and implemented by using analog circuit design techniques. Analog implementations require a variety of circuitry that comprises different passive and active electronic components like individual op-amps, comparators, analog multipliers, trigonometric function generators. Anyone who wants to experimentally investigate different structurally chaotic systems has to provide a significant amount of circuit hardware. This process may be hard and time consuming. At this stage, the question to be asked: Is there a unique analog component for implementing a universal analog chaos generator which is capable of generating the chaotic signals of nearly all analog-based chaotic systems. Fortunately, we can now answer this question positively. This analog device is FPAA (Field-Programmable Analog Array). FPAA is the analog equivalent of the FPGA (Field-Programmable Gate Array) used as programmable device in digital signal processing. FPAA is a programmable device for implementing a rich variety of systems including analog functions via dynamic reconfiguration. FPAA can be configured in real time which allows the designers to modify the design or make completely new design in real time. In this paper, we aim to show how FPAA device can be used as universal device for design and implementation of programmable analog chaos generators. For this purpose, we will introduce three FPAA-based design examples: autonomous Chua's circuit, nonautonomous MLC (Murali–Lakshmanan–Chua) circuit and a chaotic system based on a PLL (Phase Locked Loop) model.

scholarly journals Design and Implementation of Autonomous and Non-Autonomous Time-Delay Chaotic System Based on Field Programmable Analog Array

Entropy ◽  
2019 ◽  
Vol 21 (5) ◽  
pp. 437
Author(s):  
Han-Ping Hu ◽  
Xiao-Hui Liu ◽  
Fei-Long Xie
Keyword(s):  
Time Series ◽  
Time Delay ◽  
Lyapunov Exponents ◽  
Chaotic Systems ◽  
Analog Circuit ◽  
Programmable Analog ◽  
Large Numbers ◽  
Field Programmable ◽  
Programmable Device ◽  
Field Programmable Analog Array

Time-delay chaotic systems can have hyperchaotic attractors with large numbers of positive Lyapunov exponents, and can generate highly stochastic and unpredictable time series with simple structures, which is very suitable as a secured chaotic source in chaotic secure communications. But time-delay chaotic systems are generally designed and implemented by using analog circuit design techniques. Analog implementations require a variety of electronic components and can be difficult and time consuming. At this stage, we can now solve this question by using FPAA (Field-Programmable Analog Array). FPAA is a programmable device for implementing multiple analog functions via dynamic reconfiguration. In this paper, we will introduce two FPAA-based design examples: An autonomous Ikeda system and a non-autonomous Duffing system, to show how a FPAA device is used to design programmable analog time-delay chaotic systems and analyze Shannon entropy and Lyapunov exponents of time series output by circuit and simulation systems.

Self-Replicating and Self-Repairing Multicellular Automata

1998 ◽  
Vol 4 (3) ◽  
pp. 259-282 ◽  
Author(s):  
Gianluca Tempesti ◽  
Daniel Mange ◽  
André Stauffer
Keyword(s):  
Field Programmable Gate Array ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Massively Parallel ◽  
Complex Behavior ◽  
Reconfigurable Logic ◽  
Computing Systems ◽  
Field Programmable ◽  
Self Replication ◽  
Biological Organisms

Biological organisms are among the most intricate structures known to man, exhibiting highly complex behavior through the massively parallel cooperation of numerous relatively simple elements, the cells. As the development of computing systems approaches levels of complexity such that their synthesis begins to push the limits of human intelligence, engineers are starting to seek inspiration in nature for the design of computing systems, both at the software and at the hardware levels. We present one such endeavor, notably an attempt to draw inspiration from biology in the design of a novel digital circuit: a field-programmable gate array (FPGA). This reconfigurable logic circuit will be endowed with two features motivated and guided by the behavior of biological systems: self-replication and self-repair.

scholarly journals A Multi-Core Controller for an Embedded AI System Supporting Parallel Recognition

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 852
Author(s):  
Suyeon Jang ◽  
Hyun Woo Oh ◽  
Young Hyun Yoon ◽  
Dong Hyun Hwang ◽  
Won Sik Jeong ◽  
...  
Keyword(s):  
Original Data ◽  
Network Resources ◽  
Stringent Requirement ◽  
Computing Systems ◽  
Security Issues ◽  
Network Bandwidth ◽  
Resource Limited ◽  
System Use ◽  
Field Programmable ◽  
Client System

Recent advances in artificial intelligence (AI) technology encourage the adoption of AI systems for various applications. In most deployments, AI-based computing systems adopt the architecture in which the central server processes most of the data. This characteristic makes the system use a high amount of network bandwidth and can cause security issues. In order to overcome these issues, a new AI model called federated learning was presented. Federated learning adopts an architecture in which the clients take care of data training and transmit only the trained result to the central server. As the data training from the client abstracts and reduces the original data, the system operates with reduced network resources and reinforced data security. A system with federated learning supports a variety of client systems. To build an AI system with resource-limited client systems, composing the client system with multiple embedded AI processors is valid. For realizing the system with this architecture, introducing a controller to arbitrate and utilize the AI processors becomes a stringent requirement. In this paper, we propose an embedded AI system for federated learning that can be composed flexibly with the AI core depending on the application. In order to realize the proposed system, we designed a controller for multiple AI cores and implemented it on a field-programmable gate array (FPGA). The operation of the designed controller was verified through image and speech applications, and the performance was verified through a simulator.

Implementations of Modified Chaotic Neural Models with Analog Reconfigurable Hardware

2014 ◽  
Vol 24 (04) ◽  
pp. 1450046
Author(s):  
Nimet Korkmaz ◽  
Recai Kilic
Keyword(s):  
Neural Network ◽  
Neural Models ◽  
Neuron Models ◽  
Chaotic Neural Network ◽  
Programmable Analog ◽  
Field Programmable ◽  
Programmable Device ◽  
Chaotic Neuron ◽  
Reconfigurable Device ◽  
Field Programmable Analog Array

This paper focuses on implementations of two modified Aihara's chaotic neuron models and a simple chaotic neural network constructed with two chaotic neurons in a programmable and reconfigurable manner with an analog programmable device, FPAA (Field Programmable Analog Array). After testing the chaotic behaviors of two chaotic neuron models and a simple chaotic neural network through numerical analyses that consist of time domain responses, phase portrait illustrations and bifurcation diagrams, the experimental setup is constructed with a FPAA device. The parametric adjustments of chaotic neural structures are possible with the proposed flexible design methodology and different chaotic neuron models are constructed on the same reconfigurable device without any hardware changes. Experimental results verify the dynamic behaviors of these chaotic neural structures and demonstrate the efficiency of programmable implementations.

scholarly journals A Design of Intel’s IXP Meant for Embedded Systems

2019 ◽  
Vol 8 (2) ◽  
pp. 3476-3482
Keyword(s):  
Embedded System ◽  
Integrated Circuit ◽  
General Purpose ◽  
Point Of View ◽  
Computing Systems ◽  
General Purpose Processor ◽  
Network Applications ◽  
Field Programmable ◽  
Application Specific Integrated Circuit ◽  
Application Specific

Technologies to design an embedded system can be of three types: processor technology, IC technology & design technology. Billions of computing systems are built every year for a variety of purpose. They are built within larger electronic devices. These systems perform a one particular function on regular basis. These systems do not recognized by the device’s user. These systems are known as embedded system. Broad categories for system implementation are: Application Specific Integrated Circuit, Field Programmable Gate Array, CoProcessor, Application Specific Instruction Processor and General Purpose Processor. From the network processor’s designing point of view, it is very important to understand the preliminary characteristics of network applications which are generally based on address lookup, pattern matching, and queuing management which is further classified as Control plane and Data Plane processing.

Sign in / Sign up

Export Citation Format

Share Document