scholarly journals Good 150°C retention and fast erase characteristics in charge-trap-engineered memory having a scaled Si3N4 layer

Author(s):  
S. H. Lina ◽  
Albert Chin ◽  
F. S. Yeh ◽  
S. P. McAlister
Keyword(s):  
Author(s):  
C.Q. Chen ◽  
G.B. Ang ◽  
Z.X. Xing ◽  
Y.N. Hua ◽  
Z.Q. Mo ◽  
...  

Abstract Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.


Author(s):  
Jong-Moon Choi ◽  
Do-Wan Kwon ◽  
Je-Joong Woo ◽  
Eun-Je Park ◽  
Kee-Won Kwon

Author(s):  
Ting Cheng ◽  
Jianquan Jia ◽  
Lei Jin ◽  
Xinlei Jia ◽  
Shiyu Xia ◽  
...  

Crystals ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 70
Author(s):  
Minkyung Kim ◽  
Eunpyo Park ◽  
In Soo Kim ◽  
Jongkil Park ◽  
Jaewook Kim ◽  
...  

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS2 channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al2O3 and SiO2) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.


2009 ◽  
Vol 30 (2) ◽  
pp. 171-173 ◽  
Author(s):  
C. Sandhya ◽  
U. Ganguly ◽  
N. Chattar ◽  
C. Olsen ◽  
S.M. Seutter ◽  
...  

Author(s):  
Zongliang Huo ◽  
Seungjae Baik ◽  
Shieun Kim ◽  
In-seok Yeo ◽  
U-in Chung ◽  
...  

Author(s):  
James Pak ◽  
Chun Chen ◽  
Kuo-Tung Chang ◽  
Shiva Shetty ◽  
Amy Tu ◽  
...  

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