Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

Abstract We propose the novel trap-assisted tunneling (TAT) model that incorporates the ability to calculate dissipation of the kinetic energy of carriers propagating in the conduction or valence band. The proposed model allows us to evaluate capture efficiency (or the capture cross section) of carriers injected into the SiN charge trap layer via Fowler-Nordheim tunneling. By applying our TAT model to large planar Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) capacitors, experimental data showing that electron capture efficiency depends on the tunnel oxide thickness are physically interpreted. Furthermore, 3-dimensional technology computer-aided design (TCAD) simulation using SiN trap parameters roughly extracted from planar MONOS data shows that the calculated incremental step pulse programming characteristics of the charge trap memory (CTM) prototype device are comparable with measured data. We have found that additional time to calculate SiN trap charges is less than only 5 % of all remaining calculation time.

Download Full-text

Memory characteristics of multilayer structures with lanthanum-aluminate charge trap by fowler-nordheim tunneling

2010 3rd International Nanoelectronics Conference (INEC) ◽

10.1109/inec.2010.5424946 ◽

2010 ◽

Author(s):

Seung-Yong Cha ◽

Hyo-June Kim ◽

Doo-Jin Choi

Keyword(s):

Multilayer Structures ◽

Charge Trap ◽

Lanthanum Aluminate ◽

Memory Characteristics ◽

Nordheim Tunneling

Download Full-text

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

MRS Proceedings ◽

10.1557/proc-473-175 ◽

1997 ◽

Vol 473 ◽

Author(s):

Heng-Chih Lin ◽

Edwin C. Kan ◽

Toshiaki Yamanaka ◽

Simon J. Fang ◽

Kwame N. Eason ◽

...

Keyword(s):

Electric Field ◽

Three Dimensional ◽

Tunneling Current ◽

Gate Oxide ◽

Oxide Thickness ◽

Interface Roughness ◽

Normal Electric Field ◽

Surface Electric Field ◽

Tunneling Behavior ◽

Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

Download Full-text

Non-Visible Defect Analysis of OTP Device

ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2011p0198 ◽

2011 ◽

Author(s):

C.Q. Chen ◽

G.B. Ang ◽

Z.X. Xing ◽

Y.N. Hua ◽

Z.Q. Mo ◽

...

Keyword(s):

Trap Center ◽

Data Retention ◽

Auger Analysis ◽

Cross Sectional ◽

Critical Dimensions ◽

Charge Trap ◽

Root Cause ◽

Transmission Electron ◽

Electrical Analysis ◽

Visible Defect

Abstract Several product lots were found to suffer from data retention failures in OTP (one time program) devices. PFA (physical failure analysis) was performed on these devices, but nothing abnormal was observed. Cross-sectional TEM (transmission electron microscopy) revealed no physical defects or abnormal CDs (critical dimensions). In order to isolate the failed layer or location, electrical analysis was conducted. Several electrical simulation experiments, designed to test the data retention properties of OTP devices, were preformed. Meilke's method [1] was also used to differentiate between mobile ion contamination and charge trap centers. Besides Meilke's method, a new electrical analysis method was used to verify the analysis results. The results of our analysis suggests that SiN charge trap centers are the root cause for the data retention failures, and the ratio of Si/N is the key to charge trap center formation. Auger analysis was used to physically check the Si/N ratio of OTP devices. The results support our hypothesis. Subsequent DOE (Design Of Experiment) experiments also confirm our analysis results. Key Words: OTP, data retention, Non-visible defect, AFP, charge trap center, mobile ion.

Download Full-text

Implementation of an On-Chip Learning Neural Network IC Using Highly Linear Charge Trap Device

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2021.3071872 ◽

2021 ◽

pp. 1-13

Author(s):

Jong-Moon Choi ◽

Do-Wan Kwon ◽

Je-Joong Woo ◽

Eun-Je Park ◽

Kee-Won Kwon

Keyword(s):

Neural Network ◽

Linear Charge ◽

Charge Trap ◽

On Chip

Download Full-text

Investigation of Re-program Scheme in Charge Trap Based 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society ◽

10.1109/jeds.2021.3081635 ◽

2021 ◽

pp. 1-1

Author(s):

Ting Cheng ◽

Jianquan Jia ◽

Lei Jin ◽

Xinlei Jia ◽

Shiyu Xia ◽

...

Keyword(s):

Flash Memory ◽

Program Scheme ◽

Nand Flash ◽

Nand Flash Memory ◽

Charge Trap

Download Full-text

A Comparison Study on Multilayered Barrier Oxide Structure in Charge Trap Flash for Synaptic Operation

Crystals ◽

10.3390/cryst11010070 ◽

2021 ◽

Vol 11 (1) ◽

pp. 70

Author(s):

Minkyung Kim ◽

Eunpyo Park ◽

In Soo Kim ◽

Jongkil Park ◽

Jaewook Kim ◽

...

Keyword(s):

Memory Device ◽

Spike Timing ◽

Comparison Study ◽

Oxide Structure ◽

Charge Trap ◽

Synaptic Functions ◽

Essential Components ◽

Neuromorphic System ◽

A Charge ◽

Synaptic Operation

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS2 channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al2O3 and SiO2) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.

Download Full-text