Electrical characterization of FinFETs with fins formed by directed self assembly at 29 nm fin pitch using a self-aligned fin customization scheme

The use of self-assembly techniques may open new possibilities in scaling down electronic circuits to their ultimate limits. Deoxyribonucleic acid (DNA) nanotechnology has already demonstrated that it can provide valuable tools for the creation of nanostructures of arbitrary shape, therefore presenting an ideal platform for the development of nanoelectronic circuits. So far, however, the electronic properties of DNA nanostructures are mostly insulating, thus limiting the use of the nanostructures in electronic circuits. Therefore, methods have been investigated that use the DNA nanostructures as templates for the deposition of electrically conducting materials along the DNA strands. The most simple such structure is given by metallic nanowires formed by deposition of metals along the DNA nanostructures. Here, we review the fabrication and the characterization of the electronic properties of nanowires, which were created using these methods.

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Seeding, Plating and Electrical Characterization of Gold Nanowires Formed on Self-Assembled DNA Nanotubes

Molecules ◽

10.3390/molecules25204817 ◽

2020 ◽

Vol 25 (20) ◽

pp. 4817

Author(s):

Dulashani R. Ranasinghe ◽

Basu R. Aryal ◽

Tyler R. Westover ◽

Sisi Jia ◽

Robert C. Davis ◽

...

Keyword(s):

Self Assembly ◽

Electrical Characterization ◽

Metal Nanowires ◽

Gold Nanowires ◽

Nanoelectronic Devices ◽

Electronic Circuitry ◽

Self Assembled ◽

Dna Nanotubes ◽

Measured Resistivity

Self-assembly nanofabrication is increasingly appealing in complex nanostructures, as it requires fewer materials and has potential to reduce feature sizes. The use of DNA to control nanoscale and microscale features is promising but not fully developed. In this work, we study self-assembled DNA nanotubes to fabricate gold nanowires for use as interconnects in future nanoelectronic devices. We evaluate two approaches for seeding, gold and palladium, both using gold electroless plating to connect the seeds. These gold nanowires are characterized electrically utilizing electron beam induced deposition of tungsten and four-point probe techniques. Measured resistivity values for 15 successfully studied wires are between 9.3 × 10−6 and 1.2 × 10−3 Ωm. Our work yields new insights into reproducible formation and characterization of metal nanowires on DNA nanotubes, making them promising templates for future nanowires in complex electronic circuitry.

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Fabrication and temperature-dependent electrical characterization of a C-shape nanowire patterned by a DNA origami

Scientific Reports ◽

10.1038/s41598-021-81178-8 ◽

2021 ◽

Vol 11 (1) ◽

Author(s):

Türkan Bayrak ◽

Amanda Martinez-Reyes ◽

David Daniel Ruiz Arce ◽

Jeffrey Kelling ◽

Enrique C Samano ◽

...

Keyword(s):

Self Assembly ◽

Electroless Deposition ◽

Electrical Characterization ◽

Dna Origami ◽

Gold Nanowires ◽

Transport Mechanisms ◽

Temperature Dependent ◽

Weakly Coupled ◽

Different Temperatures

AbstractWe introduce a method based on directed molecular self-assembly to manufacture and electrically characterise C-shape gold nanowires which clearly deviate from typical linear shape due to the design of the template guiding the assembly. To this end, gold nanoparticles are arranged in the desired shape on a DNA-origami template and enhanced to form a continuous wire through electroless deposition. C-shape nanowires with a size below 150nm on a $${\hbox {SiO}_2}/\hbox {Si}$$ SiO 2 / Si substrate are contacted with gold electrodes by means of electron beam lithography. Charge transport measurements of the nanowires show hopping, thermionic and tunneling transports at different temperatures in the 4.2K to 293K range. The different transport mechanisms indicate that the C-shape nanowires consist of metallic segments which are weakly coupled along the wires.

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CHEMICAL AND ELECTRICAL CHARACTERIZATION OF POLYCRYSTALLINE SEMICONDUCTORS

Le Journal de Physique Colloques ◽

10.1051/jphyscol:1982124 ◽

1982 ◽

Vol 43 (C1) ◽

pp. C1-171-C1-185 ◽

Cited By ~ 5

Author(s):

L. L. Kazmerski ◽

P. E. Russell

Keyword(s):

Electrical Characterization ◽

Polycrystalline Semiconductors

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Structural and Electrical Characterization of Shaped Beam Laser Recrystallized Polysilicon on Amorphous Substrates

MRS Proceedings ◽

10.1557/proc-4-499 ◽

1981 ◽

Vol 4 ◽

Author(s):

T. J. Stultz ◽

J. F. Gibbons

Keyword(s):

Grain Size ◽

Electrical Characterization ◽

Grain Structure ◽

Electrical Characteristics ◽

Shaped Beam ◽

Beam Laser ◽

Cw Laser ◽

Amorphous Substrates ◽

Circular Beam

ABSTRACTStructural and electrical characterization of laser recrystallized LPCVD silicon films on amorphous substrates using a shaped cw laser beam have been performed. In comparing the results to data obtained using a circular beam, it was found that a significant increase in grain size can be achieved and that the surface morphology of the shaped beam recrystallized material was much smoother. It was also found that whereas circular beam recrystallized material has a random grain structure, shaped beam material is highly oriented with a <100> texture. Finally the electrical characteristics of the recrystallized film were very good when measured in directions parallel to the grain boundaries.

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Vapor Deposition Polymerization and Electrical Characterization of TPD Thin Films

IEICE Transactions on Electronics ◽

10.1587/transele.e94.c.157 ◽

2011 ◽

Vol E94-C (2) ◽

pp. 157-163 ◽

Cited By ~ 4

Author(s):

Masakazu MUROYAMA ◽

Ayako TAJIRI ◽

Kyoko ICHIDA ◽

Seiji YOKOKURA ◽

Kuniaki TANAKA ◽

...

Keyword(s):

Thin Films ◽

Vapor Deposition ◽

Electrical Characterization

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Electrical Characterization of Different Failure Modes in Sub-100 nm Devices Using Nanoprobing Technique

ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2009p0081 ◽

2009 ◽

Author(s):

E. Hendarto ◽

S.L. Toh ◽

J. Sudijono ◽

P.K. Tan ◽

H. Tan ◽

...

Keyword(s):

Electron Microscope ◽

Focused Ion Beam ◽

Failure Modes ◽

Ion Beam ◽

Electrical Characterization ◽

Nickel Silicide ◽

Fault Isolation ◽

Technology Nodes ◽

Scanning Electron

Abstract The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

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Case Studies in Atomic Force Probe Analysis

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0153 ◽

2006 ◽

Author(s):

Randal Mulder ◽

Sam Subramanian ◽

Tony Chrastecky

Keyword(s):

Failure Analysis ◽

Case Studies ◽

Light Emission ◽

Electrical Characterization ◽

Logic Circuits ◽

Contrast Imaging ◽

Atomic Force ◽

Measuring Surface ◽

Analysis Environment

Abstract The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

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Analysis of an Anomalous CMOS Transistor Exhibiting Drain to Source Leakage—Its Model and Cause

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0205 ◽

2014 ◽

Author(s):

Yuk L. Tsang ◽

Alex VanVianen ◽

Xiang D. Wang ◽

N. David Theodore

Keyword(s):

Threshold Voltage ◽

Crystalline Silicon ◽

Electrical Characterization ◽

Visual Defect ◽

Scanning Capacitance Microscopy ◽

Device Model ◽

Graphical Simulation ◽

Cmos Transistor

Abstract In this paper, we report a device model that has successfully described the characteristics of an anomalous CMOS NFET and led to the identification of a non-visual defect. The model was based on detailed electrical characterization of a transistor exhibiting a threshold voltage (Vt) of about 120mv lower than normal and also exhibiting source to drain leakage. Using a simple graphical simulation, we predicted that the anomalous device was a transistor in parallel with a resistor. It was proposed that the resistor was due to a counter doping defect. This was confirmed using Scanning Capacitance Microscopy (SCM). The dopant defect was shown by TEM imaging to be caused by a crystalline silicon dislocation.

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