Wide-range 16-phases DLL based on improved dead-zone phase detector and reduced gain charge pump

2014 ◽  
Author(s):  
Sarang Kazeminia ◽  
Sobhan Sofi Mowloodi ◽  
Khayrollah Hadidi
Keyword(s):  
Dead Zone ◽  
Charge Pump ◽  
Phase Detector ◽  
Wide Range

scholarly journals Non-linear behaviour of charge-pump phase-locked loops

2010 ◽  
Vol 8 ◽  
pp. 161-166 ◽  
Author(s):  
C. Wiegand ◽  
C. Hedayat ◽  
U. Hilleringmann
Keyword(s):  
Linear Model ◽  
Dead Zone ◽  
Charge Pump ◽  
Phase Detector ◽  
Phase Locked Loops ◽  
Time Varying ◽  
Invariant Representation ◽  
Non Linear ◽  
Linear Behaviour ◽  
Time Invariant

Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique based on the systems event-driven feature is presented, merging the logical and analogue inherent characteristics of the system. In particular, the high-grade non-linear locking process and the dead-zone are analyzed.

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

2019 ◽  
Vol 29 (09) ◽  
pp. 2050142
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Phase Detector ◽  
Total Power ◽  
Control Voltage ◽  
Frequency Range ◽  
Wide Range ◽  
Low Jitter

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump

2014 ◽  
Vol 24 (01) ◽  
pp. 1550001 ◽  
Author(s):  
Sarang Kazeminia ◽  
Sobhan Sofi Mowloodi ◽  
Khayrollah Hadidi
Keyword(s):  
Pulse Generator ◽  
Supply Voltage ◽  
Dead Zone ◽  
Charge Pump ◽  
Cmos Technology ◽  
Open Loop ◽  
Phase Detector ◽  
Total Power ◽  
Charge Pumps ◽  
Delay Locked Loop

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm2 active area in a 0.18 μm CMOS technology.

A Stable Mode-Selectable Oscillator with Variable Duty Cycle and High-Efficiency

2015 ◽  
Vol 24 (09) ◽  
pp. 1550132 ◽  
Author(s):  
Li-Ye Cheng ◽  
Xin-Quan Lai
Keyword(s):  
Duty Cycle ◽  
High Efficiency ◽  
Dynamic Performance ◽  
Operation Mode ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Process ◽  
Pump Efficiency ◽  
Stable Mode ◽  
Wide Range

A mode-selectable oscillator (OSC) with variable duty cycle for improved charge pump efficiency is proposed in this paper. The novel OSC adjusts its duty cycle according to the operation mode of the charge pump, thus improves the charge-pump efficiency and dynamic performance. The control of variable duty cycle is implemented in digital logic hence it provides robust noise immunity and instantaneous response. The OSC and the charge-pump have been implemented in a 0.6-μm 40-V CMOS process. Experimental results show that the peak efficiency is 92.7% at 200-mA load, the recovery time is less than 25 μs and load transient is 15 mV under 500-mA load variation. The system is able to work under a wide range of input voltage (V IN ) in all modes with low EMI.

scholarly journals Hard Dead Zone and Friction Modeling and Identification of a Permanent Magnet DC Motor Non-Linear Model

2020 ◽  
Vol 15 ◽  
Keyword(s):  
Permanent Magnet ◽  
Linear Model ◽  
Motor Behavior ◽  
Dead Zone ◽  
Viscous Friction ◽  
Dc Motor ◽  
Time Data ◽  
Wide Range ◽  
Non Linear ◽  
Permanent Magnet Dc Motor

The identification of a permanent magnet DC motor model including non-linearities dead zone, Coulomb friction, and viscous friction, is presented. The dead zone considered here is the so call "hard" dead zone, whereas the friction force is modeled in two different ways: first, considering the value of viscous coefficient friction as a constant and second, approximating viscous coefficient by a polynomial depending on motors rotor velocity. The polynomial representation of the viscous friction value allows it to be adjusted automatically as a function of the speed of the system, as occurs in real systems. Therefore, a model capable of better representing the real motor behavior along a wide range of operation is obtained. The non-linear model is validated and compared using real-time data obtained from Quanser's direct current motor control trainer system, using the numerical tool Matlab®/Simulink™

Sign in / Sign up

Export Citation Format

Share Document