A 80-MHz-to-410-MHz 16-Phases DLL Based on Improved Dead-Zone Open-Loop Phase Detector and Reduced-Gain Charge Pump

2014 ◽  
Vol 24 (01) ◽  
pp. 1550001 ◽  
Author(s):  
Sarang Kazeminia ◽  
Sobhan Sofi Mowloodi ◽  
Khayrollah Hadidi
Keyword(s):  
Pulse Generator ◽  
Supply Voltage ◽  
Dead Zone ◽  
Charge Pump ◽  
Cmos Technology ◽  
Open Loop ◽  
Phase Detector ◽  
Total Power ◽  
Charge Pumps ◽  
Delay Locked Loop

In this paper, a low jitter 16-phases delay locked loop (DLL) is proposed based on a simple and sensitive phase detector (PD). Dead-zone of the proposed PD is improved in compare to the conventional structures where the pulse generator postpones PD response and reduces the sensitivity. Also, the conventional structure of charge pumps is modified to inject small charge throughout the continuous outputs of PD. Smaller bias current is provided in charge pump via subtracting tail currents of intentionally mismatched differential pairs. Duty cycle of output differential phases is adjusted to around 50% using common mode setting strategy on delay elements. Simulation results confirm that DLL loop can provide 16-phases in frequency range of 80 to 410 MHz, consuming total power of 3.5 and 5.6 mW, respectively. The dead-zone of PD is also reduced from 80 to 14 ps when the pulse generator section is eliminated. Also, RMS jitter of about 45 and 1.76 ps are obtained at 80 and 410 MHz, respectively, when the supply voltage is subject to around 40 mV peak-to-peak noise disturbances. The proposed DLL can be implemented in less than 0.05 mm2 active area in a 0.18 μm CMOS technology.

Precharged Phase Detector with Zero Dead-Zone and Minimal Blind-Zone

2017 ◽  
Vol 26 (11) ◽  
pp. 1750179 ◽  
Author(s):  
Goran Nikolić ◽  
Goran Jovanović ◽  
Mile Stojčev ◽  
Tatjana Nikolić
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Dead Zone ◽  
Building Blocks ◽  
Cmos Technology ◽  
Phase Detector ◽  
Detection Range ◽  
Delay Locked Loop ◽  
Blind Zone ◽  
Bicmos Technology

A precharged CMOS high-performance phase frequency detector (PFD) circuit is presented in this paper. The PFD consists of two identical building blocks. Each PFD block generates UP or DOWN signal and consists of [Formula: see text]- and [Formula: see text]-precharge stages connected in cascade. The proposed PFD circuit has no feedback path and has zero dead-zone in the phase characteristic, what is important in low jitter applications. It also has minimal blind-zone (extended input detection range) close to the limit imposed by the used CMOS technology. The PFD is designed in 0.13[Formula: see text][Formula: see text]m BiCMOS technology and has 1.8[Formula: see text]V supply voltage. The simulation results of blind-zone values are within the range from [Formula: see text] for 1[Formula: see text]GHz up to [Formula: see text] for 8[Formula: see text]GHz. This circuit can be used in applications for high-frequency and low-power delay locked loop and phase locked loop circuits, effectively.

A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology

2019 ◽  
Vol 29 (09) ◽  
pp. 2050142
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Charge Pump ◽  
Cmos Technology ◽  
Wide Frequency Range ◽  
Phase Detector ◽  
Total Power ◽  
Control Voltage ◽  
Frequency Range ◽  
Wide Range ◽  
Low Jitter

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6[Formula: see text]GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18-[Formula: see text][Formula: see text]m CMOS technology with supply voltage of 1.8[Formula: see text]V. The output clocks with cycle-to-cycle jitter of 2.13[Formula: see text]ps at 1.6[Formula: see text]GHz. The phase noise of VCO is [Formula: see text]137[Formula: see text]dBc/Hz at an offset of 100[Formula: see text]MHz and total power consumed by the proposed PLL is 2.63[Formula: see text]mW at 1.6[Formula: see text]GHz.

CMOS PULSE GENERATOR FOR BPSK, OOK, PAM, AND PPM MODULATIONS

2009 ◽  
Vol 18 (03) ◽  
pp. 487-495 ◽  
Author(s):  
VINCENZO STORNELLI ◽  
GIUSEPPE FERRI ◽  
KING PACE
Keyword(s):  
Remote Control ◽  
Power Consumption ◽  
Pulse Duration ◽  
Short Range ◽  
Pulse Generator ◽  
Supply Voltage ◽  
Pulse Repetition Frequency ◽  
Cmos Technology ◽  
Single Chip ◽  
Control Applications

This work presents a single chip integrated pulse generator-modulator to be utilized in a short range wireless radio sensors remote control applications. The circuit, which can generate single pulses, modulated in BPSK, OOK, PAM, and also PPM, has been developed in a standard CMOS technology (AMS 0.35 μm). Typical pulse duration is about 1 ns while pulse repetition frequency is until 200 MHz (5 ns "chip" time). The operating supply voltage is ± 2.5 V, while the whole power consumption is about 15 mW. Post-layout parametric and corner analyses have confirmed the theoretical expectations.

A 2.3 mW Multi-Frequency Clock Generator with −137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology

2019 ◽  
Vol 29 (08) ◽  
pp. 2050130 ◽  
Author(s):  
Jagdeep Kaur Sahani ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Dead Zone ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Control Voltage ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Cmos Inverter ◽  
Digital Cmos

A fast phase frequency detector (PFD) and low gain low phase noise voltage-controlled oscillator (VCO)-based phase-locked loop (PLL) design are presented in this paper. PLL works in the frequency range of 0.025–1.6[Formula: see text]GHz, targeting various SoC applications. The proposed PFD, designed using CMOS dynamic logic, is fast and improves the locking time, dead zone and blind zone in the PLL. The standard CMOS inverter gate-based pseudo differential VCO is used in the PLL. Also, CMOS inverter is used as variable capacitor to tune the frequency of VCO with control voltage. The proposed PLL is designed in a 180[Formula: see text]nm CMOS process with supply voltage of 1.8[Formula: see text]V. The phase noise of VCO is [Formula: see text][Formula: see text]dBc/Hz at an offset frequency of 100[Formula: see text]MHz. The reference clock of 25[Formula: see text]MHz synthesizes the output clock of 1.6[Formula: see text]GHz with rms jitter of 0.642[Formula: see text]ps.

scholarly journals Non-linear behaviour of charge-pump phase-locked loops

2010 ◽  
Vol 8 ◽  
pp. 161-166 ◽  
Author(s):  
C. Wiegand ◽  
C. Hedayat ◽  
U. Hilleringmann
Keyword(s):  
Linear Model ◽  
Dead Zone ◽  
Charge Pump ◽  
Phase Detector ◽  
Phase Locked Loops ◽  
Time Varying ◽  
Invariant Representation ◽  
Non Linear ◽  
Linear Behaviour ◽  
Time Invariant

Abstract. The analysis of the mixed analogue and digital structure of charge-pump phase-locked loops (CP-PLL) is a challenge in modelling and simulation. In most cases the system is designed and characterized using its continuous linear model or its discrete linear model neglecting its non-linear switching behaviour. I.e., the time-varying model is approximated by a time-invariant representation using its average dynamics. Depending on what kind of phase detector is used, the scopes of validity of these approximations are different. Here, a preeminent characterization and simulation technique based on the systems event-driven feature is presented, merging the logical and analogue inherent characteristics of the system. In particular, the high-grade non-linear locking process and the dead-zone are analyzed.

Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC

2019 ◽  
Vol 29 (05) ◽  
pp. 2050073
Author(s):  
Ashima Gupta ◽  
Anil Singh ◽  
Alpana Agarwal
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Total Power ◽  
Clock Frequency ◽  
Voltage Comparator ◽  
Flash Adc ◽  
Differential Voltage ◽  
Place And Route ◽  
Eda Tools

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180[Formula: see text]nm CMOS technology with 1.8[Formula: see text]V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43[Formula: see text]dB, 25.2[Formula: see text]dB and 30.1[Formula: see text]dB, respectively at 33.20[Formula: see text]MHz input frequency and 200[Formula: see text]MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14[Formula: see text]mW. The calculated value of DNL and INL is [Formula: see text] LSB and [Formula: see text] LSB respectively.

scholarly journals A Highly Linear Low-Noise Transimpedance Amplifier for Indoor Fiber-Wireless Remote Antenna Units

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 437 ◽  
Author(s):  
Guillermo Royo ◽  
Antonio D. Martinez-Perez ◽  
Carlos Sanchez-Azqueta ◽  
Concepcion Aldea ◽  
Santiago Celma
Keyword(s):  
Cmos Technology ◽  
Antenna System ◽  
Open Loop ◽  
Low Noise ◽  
Total Power ◽  
Transimpedance Amplifier ◽  
Optimized Design ◽  
Error Vector Magnitude ◽  
Digitally Programmable ◽  
Total Power Consumption

This article presents an optimized design of a low-noise transimpedance amplifier (TIA) with high linearity for use in the downlink receiver of a remote antenna unit (RAU). The aim of this design is to be used in a cost-effective indoor distributed antenna system (DAS) for WLAN transmission using a mixed fiber-wireless system. The circuit topology consists of a fully differential shunt–shunt feedback TIA with digitally programmable transimpedance. An open-loop gain compensation technique is used to maintain stability and constant bandwidth (BW). The TIA has been fabricated in 65 nm CMOS technology with a 1.2 V voltage supply. The total power consumption of the TIA is 6 mW. A complete electrical and optical characterization with a 1550 nm PIN photodiode has been performed to demonstrate the reliable 54 Mb/s 802.11a WLAN transmission achieved with an error vector magnitude (EVM) lower than 3% for a 20 dB optical input range.

DESIGN OF MODIFIED FOUR-PHASE CMOS CHARGE PUMPS FOR LOW-VOLTAGE FLASH MEMORIES

2002 ◽  
Vol 11 (04) ◽  
pp. 393-403 ◽  
Author(s):  
HONGCHIN LIN ◽  
NAI-HSIEN CHEN ◽  
JAINHAO LU
Keyword(s):  
Power Efficiency ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Flash Memories ◽  
Clock Generation ◽  
Charge Pumps ◽  
Main Charge

A new four-phase clock scheme for the four-phase charge pumping circuits using standard 0.5 μm CMOS technology at low supply voltages to generated high boosted voltages is proposed. Boosted clocks without high drivability are applied on the capacitors coupled to the gates of the main charge transfer transistors to compensate body effects. Thus, the high-voltage clock generation circuit can be easily achieved for clock frequency of 10 MHz. Due to the nearly ideal pumping gain per stage, the design methodology to optimize power efficiency is also presented. With the new clock scheme, it can efficiently pump to 9 V at supply voltage of 1 V using 10 stages by simulations, while pump to 4.7 V at supply voltage of 1.5 V using four stages by measurements.

scholarly journals 60 GHz Front-End Components for Broadband Wireless Communication in 130 nm CMOS Technology

2016 ◽  
Vol 21 (1) ◽  
pp. 67-77
Author(s):  
Vasilis Kolios ◽  
Konstantinos Giannakidis ◽  
Grigorios Kalivas
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Total Power ◽  
Spectral Space ◽  
60 Ghz ◽  
Front End ◽  
Total Power Consumption ◽  
5 Ghz

Abstract The over 5 GHz available spectral space allocated worldwide around the 60 GHz band, is very promising for very high data rate wireless short-range communications. In this article we present two key components for the 60 GHz front-end of a transceiver, in 130 nm RF CMOS technology: a single-balanced mixer with high Conversion Gain (CG), reduced Noise Figure (NF) and low power consumption, and an LC cross-coupled Voltage Controlled Oscillator (VCO) with very good linearity, with respect to Vctrl, and very low Phase Noise (PN). In both circuits, custom designed inductors and a balun structure for the mixer are employed, in order to enhance their performance. The VCO’s inductor achieves an inductance of 198 pH and a quality factor (Q) of 30, at 30 GHz. The balun shows less than 1o Phase Imbalance (PI) and less than 0.2 dB Amplitude Imbalance (AI), from 57 to 66 GHz. The mixer shows a CG greater than 15 dB and a NF lower than 12 dB. In addition, the VCO achieves a Phase Noise lower than -106 dBc/Hz at 1 MHz offset, and shows great linearity for the entire band. Both circuits are biased with a 1.2 V supply voltage and the total power consumption is about 10.6 mW for the mixer and 10.92 mW for the VCO.

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