On-Chip Air-Gap Fabrication Using A New Sacrificial Polymer for Ultra Low-k Dielectrics

2006 ◽  
Author(s):  
S. Park ◽  
J. Krotine ◽  
S.A. Bidstrup Allen ◽  
P.A. Kohl
Keyword(s):  
Air Gap ◽  
On Chip ◽  
Low K

Integration of Al-Fill Processes for Contacts and VIAS

1996 ◽  
Vol 427 ◽  
Author(s):  
H. J. Barth
Keyword(s):  
High Pressure ◽  
Chip Design ◽  
Size And Shape ◽  
Future Developments ◽  
Pattern Density ◽  
New Challenges ◽  
On Chip ◽  
Damascene Interconnects ◽  
Low K ◽  
Electrical Data

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.

Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks

2013 ◽  
Vol 592-593 ◽  
pp. 563-568
Author(s):  
Christoph Sander ◽  
Martin Gall ◽  
Kong Boon Yeap ◽  
Ehrenfried Zschech
Keyword(s):  
Computing Time ◽  
Orientation Dependence ◽  
Chip Design ◽  
Simulation Methodology ◽  
3D Packaging ◽  
Internal Mechanical Stress ◽  
On Chip ◽  
Physics Based Simulation ◽  
Low K ◽  
Chip Analysis

Managing the emerging internal mechanical stress in chips particularly if they are 3D-tscked is a key task to maintain performance and reliability of microelectronic products. Hence, a strong need of a physics-based simulation methodology/flow emerges. This physics-based simulation, however, requires materials parameters with high accuracy. A full-chip analysis can then be performed, balancing the need for local resolution and computing time. Therefore, effective composite-type materials data for several regions of interest are needed. Advanced techniques to measure FEA-and design-relevant properties such as local and effective Youngs modulus and effective CTE values were developed and described in this paper. These data show a clear orientation dependence, caused by the chip design.

Modeling of Thermo-Mechanical Stresses in Copper Interconnect/Low-k Dielectric Systems

2005 ◽  
Author(s):  
Y.-L. Shen
Keyword(s):  
Structural Integrity ◽  
Temperature Response ◽  
Future Generation ◽  
Interface Fracture ◽  
Deformation Pattern ◽  
Barrier Layers ◽  
Copper Interconnect ◽  
On Chip ◽  
Interconnect Systems ◽  
Low K

Systematic finite element analyses are carried out to model the thermomechanical stresses in on-chip copper interconnect systems. Constitutive behavior of encapsulated copper films, determined by experimentally measuring the stress-temperature response during thermal cycling, is used in the model for predicting stresses in copper interconnect/low-k dielectric structures. Various combinations of oxide and polymer-based low-k dielectric schemes are considered. The evolution of stresses and deformation pattern in the dual-damascene copper, barrier layers, and the dielectrics is seen to have direct connections to the structural integrity of contemporary and future-generation devices. In particular, stresses experienced by the thin barrier layers and the mechanically weak low-k dielectrics are critically assessed. A parametric analysis on the influence of low-k material properties is also conducted. Practical implications in reliability issues such as voiding, interface fracture, electromigration and dielectric failure are discussed.

Advanced sub 0.13µm Cu Devices – Failure Analysis and Circuit Edit With Improved FIB Chemical Processes and Beam Characteristics

2002 ◽  
Author(s):  
J. David Casey ◽  
Thomas J. Gannon ◽  
Alex Krechmer ◽  
David Monforte ◽  
Nicholas Antoniou ◽  
...  
Keyword(s):  
Failure Analysis ◽  
High Speed ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Chemical Processes ◽  
Design Verification ◽  
End Point Detection ◽  
On Chip ◽  
Point Detection ◽  
Low K

Abstract Advances in FIB (focused ion beam) chemical processes and in the Ga (gallium) beam profile are discussed; these advances are necessary for the successful failure analysis, circuit edit and design verification of advanced, sub-0.13µm Cu devices. Included in this article are: a novel FIB method (CopperRx) for smoothly milling thick, large grained Cu lines; H2O and O2 processes for cleanly cutting thin, smaller grained Cu lines, thereby forming electrically open interconnects; a XeF2 GAE (gas assisted etching) process for etching low k, CVD dielectrics such as F and C doped SiO2; H2O and XeF2 GAE processes for etching low k, spin-on, organic dielectrics such as SiLK; a recently developed recipe for the deposition of SiO2 based material with intermediate resistivity (106 µohm·cm) which is useful in the design verification of frequency sensitive, high speed analog and SOC (system on chip) circuits; an improved, more Gaussian Ga beam with less current density in the beam tails (VisION column) which provides higher resolution, real time images needed for end-point detection on sub 0.13µm features during milling.

Sign in / Sign up

Export Citation Format

Share Document