Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

2002 ◽  
Author(s):  
J. Burns ◽  
L. McIlrath ◽  
C. Keast ◽  
C. Lewis ◽  
A. Loomis ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Three Dimensional ◽  
High Bandwidth

Minimal Buffer Insertion Based Low Power Clock Tree Synthesis for 3D Integrated Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650142 ◽  
Author(s):  
Kamineni Sumanth Kumar ◽  
John Reuben
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Three Dimensional ◽  
Buffer Insertion ◽  
Clock Skew ◽  
Clock Tree ◽  
Clock Tree Synthesis ◽  
3D Integrated Circuits ◽  
Tree Synthesis

Three-Dimensional (3D) Integrated Circuits (ICs) offers integrating capabilities of ‘More than Moore’ while overcoming CMOS scaling limitations, providing the advantages of low power, high performance and reduced costs. The design of the Clock Distribution Network (CDN) for a 3D IC has to be done meticulously to guarantee reliable operation. In the design of the CDN, clock buffers are crucial units that affect the clock skew, slew and power dissipated by the clock tree. In this paper, we propose a two-stage buffering technique that inserts clock buffers for slew control and skew minimization. Such a buffering technique decreases the number of buffers and power dissipated in the clock tree when compared to previous works which were inserting buffers primarily for slew control. We incorporate the proposed buffering technique into the 3D clock tree synthesis algorithm of previous work and evaluate the performance of the clock tree for both single Through-Silicon Vias (TSV) and mutiple TSV approach. When evaluated on IBM benchmarks (r1-r5), our buffering technique results in 25–28% reduction in buffer count and 25–29% reduction in power for single TSV-based 3D CDN. For multi-TSV approach, the performance of our work is even better:around 31–38% reduction in buffer count and 32–39% reduction in power.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

scholarly journals Fabrication of Eutectic Ga-In Nanowire Arrays Based on Plateau–Rayleigh Instability

Molecules ◽  
2021 ◽  
Vol 26 (15) ◽  
pp. 4616
Author(s):  
Takashi Ikuno ◽  
Zen Somei
Keyword(s):  
Integrated Circuits ◽  
Substrate Surface ◽  
Three Dimensional ◽  
Average Diameter ◽  
Nanowire Arrays ◽  
Scanning Probe ◽  
Rayleigh Instability ◽  
Simple Method ◽  
Flat Substrate ◽  
Metal Nanowire

We have developed a simple method of fabricating liquid metal nanowire (NW) arrays of eutectic GaIn (EGaIn). When an EGaIn droplet anchored on a flat substrate is pulled perpendicular to the substrate surface at room temperature, an hourglass shaped EGaIn is formed. At the neck of the shape, based on the Plateau–Rayleigh instability, the EGaIn bridge with periodically varying thicknesses is formed. Finally, the bridge is broken down by additional pulling. Then, EGaIn NW is formed at the surface of the breakpoint. In addition, EGaIn NW arrays are found to be fabricated by pulling multiple EGaIn droplets on a substrate simultaneously. The average diameter of the obtained NW was approximately 0.6 μm and the length of the NW depended on the amount of droplet anchored on the substrate. The EGaIn NWs fabricated in this study may be used for three-dimensional wiring for integrated circuits, the tips of scanning probe microscopes, and field electron emission arrays.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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