Study on the ESD-induced gate-oxide breakdown and the protection solution in 28nm high-k metal-gate CMOS technology

Author(s):  
Chun-Yu Lin ◽  
Ming-Dou Ker ◽  
Pin-Hsin Chang ◽  
Wen-Tai Wang
2015 ◽  
Vol 15 (1) ◽  
pp. 382-385
Author(s):  
Jun Hee Cho ◽  
Sang-Ick Lee ◽  
Jong Hyun Kim ◽  
Sang Jun Yim ◽  
Hyung Soo Shin ◽  
...  

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000116-000121
Author(s):  
K. Grella ◽  
S. Dreiner ◽  
H. Vogt ◽  
U. Paschen

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.


2010 ◽  
Vol 45 (1) ◽  
pp. 103-110 ◽  
Author(s):  
Yih Wang ◽  
Uddalak Bhattacharya ◽  
Fatih Hamzaoglu ◽  
Pramod Kolar ◽  
Yong-Gee Ng ◽  
...  

2009 ◽  
Vol 1155 ◽  
Author(s):  
Serge Oktyabrsky ◽  
Padmaja Nagaiah ◽  
Vadim Tokranov ◽  
Sergei Koveshnikov ◽  
Michael Yakimov ◽  
...  

AbstractGroup III-V semiconductor materials are being studied as potential replacements for conventional CMOS technology due to their better electron transport properties. However, the excess scattering of carriers in MOSFET channel due to high-k gate oxide interface significantly depreciates the benefits of III-V high-mobility channel materials. We present results on Hall electron mobility of buried QW structures influenced by remote scattering due to InGaAs/HfO2 interface. Mobility in In0.77Ga0.23As QWs degraded from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope changed from T-1.2 to almost T+1.0 in 77-300 K range when the barrier thickness is reduced from 50 to 0 nm. This mobility change is attributed to remote Coulomb scattering due to charges and dipoles at semiconductor/oxide interface. Elimination of the InGaAs/HfO2 interface via introduction of SiOx interface layer formed by oxidation of thin a-Si passivation layer was found to improve the channel mobility. The mobility vs. sheet carrier density shows the maximum close to 2×1012 cm-2.


Author(s):  
B. Doris ◽  
Y.H. Kim ◽  
B.P. Linder ◽  
M. Steen ◽  
V. Narayanan ◽  
...  

2012 ◽  
Vol 48 (25) ◽  
pp. 1627-1629 ◽  
Author(s):  
R. Ouhachi ◽  
A. Pottrain ◽  
D. Gloria ◽  
C. Gaquière ◽  
D. Ducatteau ◽  
...  
Keyword(s):  
High K ◽  

Author(s):  
C.-H. Jan ◽  
M. Agostinelli ◽  
H. Deshpande ◽  
M. A. El-Tanani ◽  
W. Hafez ◽  
...  

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