Electron Scattering in Buried InGaAs MOSFET Channel with HfO2 Gate Oxide

2009 ◽  
Vol 1155 ◽  
Author(s):  
Serge Oktyabrsky ◽  
Padmaja Nagaiah ◽  
Vadim Tokranov ◽  
Sergei Koveshnikov ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
High Mobility ◽  
Gate Oxide ◽  
Cmos Technology ◽  
Interface Layer ◽  
Oxide Interface ◽  
Channel Mobility ◽  
Group Iii ◽  
High K ◽  
Electron Transport Properties ◽  
Group Iii V Semiconductor

AbstractGroup III-V semiconductor materials are being studied as potential replacements for conventional CMOS technology due to their better electron transport properties. However, the excess scattering of carriers in MOSFET channel due to high-k gate oxide interface significantly depreciates the benefits of III-V high-mobility channel materials. We present results on Hall electron mobility of buried QW structures influenced by remote scattering due to InGaAs/HfO2 interface. Mobility in In0.77Ga0.23As QWs degraded from 12000 to 1200 cm2/V-s and the mobility vs. temperature slope changed from T-1.2 to almost T+1.0 in 77-300 K range when the barrier thickness is reduced from 50 to 0 nm. This mobility change is attributed to remote Coulomb scattering due to charges and dipoles at semiconductor/oxide interface. Elimination of the InGaAs/HfO2 interface via introduction of SiOx interface layer formed by oxidation of thin a-Si passivation layer was found to improve the channel mobility. The mobility vs. sheet carrier density shows the maximum close to 2×1012 cm-2.

High Mobility ZnO thin film transistors using the novel deposition of high-k dielectrics

2011 ◽  
Vol 1315 ◽  
Author(s):  
D. K. Ngwashi ◽  
R. B. M. Cross ◽  
S. Paul ◽  
Andrian P. Milanov ◽  
Anjana Devi
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Performance Metrics ◽  
Chemical Vapour ◽  
High Mobility ◽  
Hafnium Dioxide ◽  
Organic Chemical ◽  
Channel Mobility ◽  
High K ◽  
Metal Organic

ABSTRACTIn order to investigate the performance of ZnO-based thin film transistors (ZnO-TFTs), we fabricate devices using amorphous hafnium dioxide (HfO2) high-k dielectrics. Sputtered ZnO was used as the active channel layer, and aluminium source/drain electrodes were deposited by thermal evaporation, and the HfO2 high-k dielectrics are deposited by metal-organic chemical vapour deposition (MOCVD). The ZnO-TFTs with high-k HfO2 gate insulators exhibit good performance metrics and effective channel mobility which is appreciably higher in comparison to SiO2-based ZnO TFTs fabricated under similar conditions. The average channel mobility, turn-on voltage, on-off current ratio and subthreshold swing of the high-k TFTs are 31.2 cm2V-1s-1, -4.7 V, ~103, and 2.4 V/dec respectively. We compared the characteristics of a typical device consisting of HfO2 to those of a device consisting of thermally grown SiO2 to examine their potential for use as high-k dielectrics in future TFT devices.

Development of III-Sb Technology for p-Channel MOSFETs

2014 ◽  
Vol 23 (03n04) ◽  
pp. 1450015 ◽  
Author(s):  
Andrew Greene ◽  
Shailesh Madisetti ◽  
Michael Yakimov ◽  
Vadim Tokranov ◽  
Serge Oktyabrsky
Keyword(s):  
Quantum Wells ◽  
Supply Voltage ◽  
High Mobility ◽  
Hole Mobility ◽  
State Density ◽  
Injection Velocity ◽  
Oxide Interface ◽  
Group Iii ◽  
Multiple Challenges ◽  
Activation Annealing

Alternative channel materials with superior transport properties over conventional silicon based systems are required for supply voltage scaling in CMOS circuits. Group III- Sb 's are a candidate for high mobility p-channel applications due to a low hole effective mass, large injection velocity in scaled devices and the ability to achieve enhanced hole mobility in strained quantum wells (QW). Multiple challenges in antimonide MOSFET development are assessed and developed technologies were implemented into p-channel MOSFET fabrication with a low thermal processing budget of 350°C. These challenges include growth of “bulk” GaSb and bi-axial compressively strained In x Ga 1-x Sb QW channels on lattice mismatched GaAs substrates, reduction of interface trap state density (Dit) at the III- Sb /high-k oxide interface and avoiding ion implanted source and drain contacts with high temperature activation annealing. A “self-aligned” single mask p-channel MOSFET fabrication process was developed on buried In 0.36 Ga 0.64 Sb QW channels using intermetallic source and drain contacts. The first “gate-last” MOSFET process on In 0.36 Ga 0.64 Sb QW channels with pre-grown epitaxial p++- GaSb contacts is demonstrated. InAs has been proven to be an excellent etch stop layer when using an optimized tetramethylammonium hydroxide (TMAH) etch of p++- GaSb to prevent InGaSb QW damage.

ELECTRON SCATTERING IN BURIED InGaAs/HIGH-K MOS CHANNELS

2011 ◽  
Vol 20 (01) ◽  
pp. 95-103 ◽  
Author(s):  
S. OKTYABRSKY ◽  
P. NAGAIAH ◽  
V. TOKRANOV ◽  
M. YAKIMOV ◽  
R. KAMBHAMPATI ◽  
...  
Keyword(s):  
Dominant Role ◽  
Interface Layer ◽  
Barrier Thickness ◽  
Channel Mobility ◽  
High K ◽  
Amorphous Si ◽  
Inp Substrates ◽  
Low K

Hall electron mobility in buried QW InGaAs channels, grown on InP substrates with HfO 2 gate oxide, is analyzed experimentally and theoretically as a function of top barrier thickness and composition, carrier density, and temperature. Temperature slope α in μ ~Tα dependence is changing from α=-1.1 to +1 with the reduction of the top barrier thickness indicating the dominant role of remote Coulomb scattering (RCS) in interface-related contribution to mobility degradation. Insertion of low-k SiO x interface layer formed by oxidation of thin in-situ MBE grown amorphous Si passivation layer has been found to improve the channel mobility, but at the expense of increased EOT. This mobility improvement is also consistent with dominant role of RCS. We were able to a obtain a reasonable match between experiment and simple theory of the RCS assuming the density of charges at the high-k/barrier interface to be in the range of (2-4)×1013 cm-2.

Atomic-Ratio effect of transition layer for linear mobility in poly-Si TFTs

1996 ◽  
Vol 424 ◽  
Author(s):  
M. Y. Jung ◽  
Y. H. Jung ◽  
S. S. Bae ◽  
S. M. Seo ◽  
D. G. Moon ◽  
...  
Keyword(s):  
Double Layer ◽  
Oxide Films ◽  
Single Layer ◽  
Gate Oxide ◽  
Interface Layer ◽  
Atomic Ratio ◽  
Field Effect Mobility ◽  
Oxide Interface ◽  
Oxide Deposition ◽  
Gas Ratio

AbstractPoly-Si TFTs with high field effect mobility are fabricated by using PECVD SiO2 layer deposited with a new method: two-step (graded) oxide deposition. To adjust stoichiometry of the poly-Si/oxide interface and the bulk oxide layer, the double layer oxide films were deposited. The oxide films near the interface were deposited with high N2O/SiH4 gas ratio to obtain the stoichiometric layer for good matching between poly-Si and SiO2. The remaining bulk oxide films were deposited with low N2O/SiH4 gas ratio. The composition of the bulk oxide film was measured by using ESCA and the interface layer was analized with ESR. The poly-Si TFT with the double layer gate oxide resulted to the better performance than conventional TFT wth single layer gate oxde.

High-Mobility SiC MOSFETs Using a Thin-SiO2/Al2O3 Gate Stack

2018 ◽  
Vol 924 ◽  
pp. 494-497 ◽  
Author(s):  
Jesus Urresti ◽  
Faiz Arith ◽  
Konstantin Vassilevski ◽  
Amit Kumar Tiwari ◽  
Sarah Olsen ◽  
...  
Keyword(s):  
High Temperature ◽  
Low Temperature ◽  
High Mobility ◽  
Gate Oxide ◽  
Interface Traps ◽  
Gate Stack ◽  
Mos Capacitors ◽  
Channel Mobility

We report the development of a low-temperature (600 °C) gate oxidation approach to minimize the density of interface traps (DIT) at the SiC/SiO2interface, ultimately leading to a significantly higher channel mobility in SiC MOSFETs of 81 cm2·V-1·s-1, >11x higher than devices fabricated alongside but with a conventional 1150 °C gate oxide. We further report on the comparison made between the DITand channel mobilities of MOS capacitors and n-MOSFETs fabricated using the low-and high-temperature gate oxidation.

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

Nitrogen Implantation and Diffusion in Silicon

1999 ◽  
Vol 568 ◽  
Author(s):  
Lahir Shaik Adam ◽  
Mark E. Law ◽  
Omer Dokumaci ◽  
Yaser Haddara ◽  
Cheruvu Murthy ◽  
...  
Keyword(s):  
Silicon Oxide ◽  
Gate Oxide ◽  
Nitrogen Diffusion ◽  
Nitrogen Implantation ◽  
Oxide Interface ◽  
Diffusion Behavior ◽  
Czochralski Silicon ◽  
Interface Modeling ◽  
And Diffusion ◽  
Silicon Silicon

ABSTRACTNitrogen implantation can be used to control gate oxide thicknesses [1,2]. This study aims at studying the fundamental behavior of nitrogen diffusion in silicon. Nitrogen at sub-amorphizing doses has been implanted as N2+ at 40 keV and 200 keV into Czochralski silicon wafers. Furnace anneals have been performed at a range of temperatures from 650°C through 1050°C. The resulting annealed profiles show anomalous diffusion behavior. For the 40 keV implants, nitrogen diffuses very rapidly and segregates at the silicon/ silicon-oxide interface. Modeling of this behavior is based on the theory that the diffusion is limited by the time to create a mobile nitrogen interstitial.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

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