A 21.4% tuning range 13 GHz Quadrature voltage-controlled oscillator utilizing manipulatable inherent bimodal oscillation phenomenon in standard 90-nm CMOS process

Author(s):  
Shih-Chieh Shin ◽  
J Laskar
Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.


2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.


2021 ◽  
Author(s):  
Mahin Esmaeilzadeh ◽  
Yves Audet ◽  
Mohamed Ali ◽  
Mohamad Sawan

<p>We describe in the paper a ring voltage-controlled oscillator (VCO) indicating an improved phase noise over a wide range of frequency offsets and an extended frequency/voltage tuning range. The phase noise is improved by leveraging a better linearity approach, while reducing the VCO gain and maintaining wide tuning range. The proposed VCO is a block of a time-domain comparator embedded in a monitoring and readout circuit of an industrial sensor interface. An analytical model is extracted resulting in closed-form expressions for both input-referred noise and phase noise of the VCO. Employing the analytical expressions, the contributed noise and phase noise limitations are fully addressed, and all the effective factors are investigated. The prototype of the proposed VCO was implemented and fabricated in a 0.35 µm CMOS process. The integrated VCO consumes 0.903 mW from a 3.3 V supply, when running at its maximum frequency of 9.37 MHz. The measured phase noise of the proposed VCO is -147.57 dBc/Hz at 1 MHz offset from the 9.37 MHz oscillation frequency, and the occupied silicon area of circuit is 0.005 mm<sup>2</sup>.</p>


2021 ◽  
Vol 3 (4) ◽  
Author(s):  
Dileep Dwivedi ◽  
Manoj Kumar ◽  
Vandana Niranjan

AbstractThis paper presents a low-power, wide tuning range CMOS voltage-controlled oscillator with MCML (MOS current mode logic) differential delay cell. Voltage controlled oscillator (VCO) circuit is designed in TSMC 0.25 μm CMOS process. To achieve the broad frequency range concept of variable capacitance is employed in the proposed VCO circuit. Source/drain tuning voltage (Vtune) and body bias voltage (Vb) of I-MOS varactor are used to achieve variable capacitance at different I-MOS varactor widths (W). The dual control voltage of I-MOS varactor results in a tuning range from 0.528 GHz to 2.014 GHz. VCO's figure of merit (FoM) is 152.13 dBc/Hz with phase noise of −93.77 dBc/Hz at 1 MHz offset from the oscillation frequency. The proposed VCO dissipates maximum power of 3.127 mW.


Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 935 ◽  
Author(s):  
Arash Hejazi ◽  
YoungGun Pu ◽  
Kang-Yoon Lee

This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.


2019 ◽  
Vol 28 (14) ◽  
pp. 1950242
Author(s):  
Omar Faruqe ◽  
Md Tawfiq Amin

This paper presents a varactorless tunable active inductor-based voltage controlled oscillator (VCO) in 90[Formula: see text]nm CMOS process. The proposed VCO yields a wide tuning range of 116% with an output frequency of 1.19–4.46[Formula: see text]GHz for the tuning voltage of 0.3–1.5[Formula: see text]V. It consumes a low dc power ranging from 2.44[Formula: see text]mW to 4.79[Formula: see text]mW for the specified tuning range. The variation of phase noise ranges from [Formula: see text][Formula: see text]dBc/Hz to [Formula: see text][Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset with the change of tuning voltage as well as tuning frequency. The proposed varactorless VCO has a maximum Figure of Merit (FOM) of [Formula: see text][Formula: see text]dBc/Hz with a differential output power of 1.8[Formula: see text]dBm at tuning voltage of 0.7[Formula: see text]V. The elimination of varactor which abates the silicon area consumption and the minimization of the variation of performance parameters are the special outcomes of the proposed active inductor-based VCO. Comparing the performance parameters such as power consumption, FOM and tuning range, the proposed design outperforms most of the cited designs.


2011 ◽  
Vol 2011 ◽  
pp. 1-7 ◽  
Author(s):  
Yusaku Ito ◽  
Kenichi Okada ◽  
Kazuya Masu

This paper proposes a novel wideband LC-based voltage-controlled oscillator (VCO) for multistandard transceivers. The proposed VCO has a core LC-VCO and a tuning-range extension circuit, which consists of switches, a mixer, dividers, and variable gain combiners with a spurious rejection technique. The experimental results exhibit 0.98 to 6.6 GHz continuous frequency tuning with −206 dBc/Hz of FoMT, which is fabricated by using a 0.18 μm CMOS process. The frequency tuning range (FTR) is 149%, and the chip area is 800 μm × 540 μm.


2021 ◽  
Author(s):  
Sameh Soliman

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.


Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1290
Author(s):  
Jeong-Yun Lee ◽  
Gwang Sub Kim ◽  
Goo-Han Ko ◽  
Kwang-Il Oh ◽  
Jae Gyeong Park ◽  
...  

This paper proposes a new structure of 24-GHz class-C voltage-controlled oscillator (VCO) using an auto-adaptive bias technique. The VCO in this paper uses a digitally controlled circuit to eliminate the possibility of start-up failure that a class-C structure can have and has low phase noise and a wide frequency range. To expand the frequency tuning range, a 3-bit cap-bank is used and a triple-coupled transformer is used as the core inductor. The proposed class-C VCO implements a 65-nm RF CMOS process. It has a phase noise performance of −105 dBc/Hz or less at 1-MHz offset frequency and the output frequency range is from 22.8 GHz to 27.3 GHz, which consumes 8.3–10.6 mW of power. The figure-of-merit with tuning range (FoMT) of this design reached 191.1 dBc/Hz.


2021 ◽  
Author(s):  
Sameh Soliman

The current high-growth nature of digital communications demands higher speed serial communication circuits. Present day technologies barely manage to keep up with this demand, and new techniques are required to ensure that serial communication can continnue to expand and grow. The goal of this work is to optimize the performance of an essential building block of serial communication circuits, namely, the phase-locked loop (PLL), so that it can cope with today's high-speed communication. Due to its popularity, the optimization has targeted the charge-pump-based implementqation of the phase-locked loop. This goal is achieved by researching, designing, and evaluating high speed serial communication circuits. Research has involved an in-depth study of the state of the art in high-speed serial communication circuits ; high-speed, controlled oscillators, and CMOS technology. An LC, voltage-controlled oscillator (VCO) is designed in 0.18-micron, mixed-signal, 6-metal-2-poly, CMOS process. A novel tuning technique is employed to tune its output frequency. Simulation results shows that it provides quadrature and differential outputs, operates with 10 GHz center frequency, 600-MHz tuning range centered around its center frequency, and phase noise of -95 dBc/Hz at 1-MHz offset from the fundamental harmonic of its output, and draws 10 ,A of DC current from a single 1.8-V power supply. Also, it exhibits a good linearity throughout its tuning range. The new tuning technique increases the tuning range of the VCO to 6% of its center frequency compared to the 1-to-2% typical value. As its locking performance depends on the characteristic of the employed VCO and to demonstrate the effect of optimizing the tuning range of the VCO, a charge-pump PLL is designed. Simulation results shows that the PLL acquisition range is 300 MHz compared to a maximum value of 100 MHz when a conventional LC VCO is employed. Also, as a measure of its tracking range, the maximum frequency slew rate of its input has improved by 40%.


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