$\pi$ -SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology

Abstract Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

Download Full-text

Ultra-low-voltage-triggered Silicon Controlled Rectifier (ULVTSCR) ESD Protection Device for 1.2V/1.8V Application

10.21203/rs.3.rs-126594/v1 ◽

2020 ◽

Author(s):

Ruibo Chen ◽

Hongxia Liu ◽

Fei Hou ◽

Feibo Du ◽

Zixu Liu ◽

...

Keyword(s):

Low Voltage ◽

Optimization Methods ◽

Cmos Technology ◽

Protection Device ◽

Test Results ◽

Critical Dimensions ◽

Current Voltage ◽

Esd Protection ◽

Current Voltage Characteristics ◽

The Impact

Abstract High trigger voltage (Vt1) characteristic of silicon-controlled rectifier (SCR) device has limited its application in electrostatic discharge (ESD) protection of low voltage circuit, especially in advanced CMOS technologies. In this letter, an ultra-low-voltage-triggered SCR (ULVTSCR) is proposed to decrease the trigger voltage of the conventional SCR. The proposed device consists of an external NMOSs-string (ENMOSs-string), an internal NMOS (INMOS) with its gate controlled by the ENMOSs-string, and a main SCR triggered with the INMOS assistance. The ESD current-voltage characteristics of ULVTSCR has been measured with the transmission line pulsing (TLP) tester. The test results indicate that the proposed ULVTSCR possesses much lower Vt1 of ~ 5.03V as well as reduced area consumption compared to the existing optimization methods, making it highly suitable for the ESD protection for 1.2V/1.8V IO ports in CMOS technology. In addition, the impact of various critical dimensions of ULVTSCR have also been evaluated to further improve the ESD characteristics.

Download Full-text

Design of a Dual-directional Diode-triggered SCR for Low Voltage ESD Protection

IEEJ Transactions on Electronics Information and Systems ◽

10.1541/ieejeiss.140.673 ◽

2020 ◽

Vol 140 (6) ◽

pp. 673-674

Author(s):

Qiang Xu ◽

Hailian Liang ◽

Xiaofeng Gu

Keyword(s):

Low Voltage ◽

Esd Protection

Download Full-text

1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽

10.3390/electronics10050563 ◽

2021 ◽

Vol 10 (5) ◽

pp. 563

Author(s):

Jorge Pérez-Bailón ◽

Belén Calvo ◽

Nicolás Medrano

Keyword(s):

Power Consumption ◽

Dynamic Range ◽

Low Voltage ◽

Cutoff Frequency ◽

Cmos Technology ◽

Active Area ◽

Current Steering ◽

Low Pass ◽

On Chip ◽

Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

Download Full-text

Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

Journal of Low Power Electronics and Applications ◽

10.3390/jlpea11010006 ◽

2021 ◽

Vol 11 (1) ◽

pp. 6

Author(s):

Orazio Aiello

Keyword(s):

Integrated Circuits ◽

Electromagnetic Interference ◽

Low Voltage ◽

Current Source ◽

Building Blocks ◽

Cmos Technology ◽

Threshold Region ◽

Output Current ◽

Current Generator ◽

Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

Download Full-text

Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

Download Full-text