High-performance low-leakage enhancement-mode high-K dielectric GaN MOSHEMTs for energy-efficient, compact voltage regulators and RF power amplifiers for low-power mobile SoCs

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Download Full-text

Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

Journal of Computational Electronics ◽

10.1007/s10825-019-01353-z ◽

2019 ◽

Vol 18 (3) ◽

pp. 924-940 ◽

Cited By ~ 2

Author(s):

G. Thriveni ◽

Kaustab Ghosh

Keyword(s):

Theoretical Analysis ◽

Low Power ◽

Power Dissipation ◽

High Performance ◽

Double Gate ◽

Dielectric Layers ◽

High K ◽

Low Power Dissipation ◽

High K Dielectric

Download Full-text

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

10.31399/asm.cp.istfa2018p0300 ◽

2018 ◽

Author(s):

Seng Nguon Ting ◽

Hsien-Ching Lo ◽

Donald Nedeau ◽

Aaron Sinnott ◽

Felix Beaudoin

Keyword(s):

Failure Analysis ◽

High Performance ◽

Yield Loss ◽

Technology Development ◽

High Density ◽

High K ◽

Yield Learning ◽

Oxide Deposition ◽

Edge Profile ◽

High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Download Full-text

32nm gate-first high-k/metal-gate technology for high performance low power applications

2008 IEEE International Electron Devices Meeting ◽

10.1109/iedm.2008.4796770 ◽

2008 ◽

Cited By ~ 12

Author(s):

C. H. Diaz ◽

K. Goto ◽

H.T. Huang ◽

Yuri Yasuda ◽

C.P. Tsao ◽

...

Keyword(s):

Low Power ◽

High Performance ◽

Metal Gate ◽

High K

Download Full-text

Energy Efficient VLSI Based DCT Architecture with Accurate Error Compensation

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.626.127 ◽

2014 ◽

Vol 626 ◽

pp. 127-135 ◽

Cited By ~ 1

Author(s):

D. Jessintha ◽

M. Kannan ◽

P.L. Srinivasan

Keyword(s):

Low Power ◽

Energy Efficient ◽

Time Complexity ◽

High Performance ◽

Low Power Consumption ◽

Distributed Arithmetic ◽

Technology Scaling ◽

Truncation Errors ◽

History Of ◽

Technology Dependency

Discrete Cosine Transform (DCT) is commonly used in image compression. In the history of DCT, a milestone was the Distributed Arithmetic (DA) technique. Due to the technology dependency a multiplier-less computation was built with DA based technique. It occupied less area but the throughput is less. Later, due to the technology scaling, multiplier based architectures can be easily adapted for low-power and high-performance architecture. Fixed width multipliers [1]-[7] reduces hardware and time complexity. In this work, Radix 4 fixed width multiplier is adapted with DCT architecture due to low power consumption and saves 30% power. In order to reduce truncation errors caused during fixed width multiplication, an estimation circuit is designed based on conditional probability theory.

Download Full-text

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

International Journal of Nanoscience ◽

10.1142/s0219581x14500124 ◽

2014 ◽

Vol 13 (02) ◽

pp. 1450012 ◽

Cited By ~ 1

Author(s):

Manorama Chauhan ◽

Ravindra Singh Kushwah ◽

Pavan Shrivastava ◽

Shyam Akashe

Keyword(s):

Integrated Circuits ◽

Metal Oxide ◽

Low Power ◽

High Performance ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Short Channel ◽

State Dependency ◽

Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Download Full-text

Nmos Logic Circuits in Laser-Crystallized Silicon on Quartz

MRS Proceedings ◽

10.1557/proc-23-551 ◽

1983 ◽

Vol 23 ◽

Cited By ~ 1

Author(s):

A. Chiang ◽

M. H. Zarzycki ◽

W. P. Meuli ◽

N. M. Johnson

Keyword(s):

High Performance ◽

Logic Circuits ◽

Leakage Currents ◽

Enhancement Mode ◽

Low Leakage ◽

Fused Quartz ◽

Amorphous Substrates ◽

Circular Beam ◽

Processing Steps ◽

Dynamic Shift

ABSTRACTDepletion mode as well as enhancement mode n-channel thin-film transistors (TFT's) have been fabricated in CO2 laser-crystallized silicon on fused quartz. Nearly defect-free islands were obtained by using an offset circular beam to form a tilted melt interface. The optimization of subsequent processing steps to achieve simultaneously low leakage currents and voltage thresholds appropriate for depletion-load NMOS circuits involved adjustments of ion implantation and high temperature cycles with the aid of simulation. The resultant high performance silicon-gate TFT's have led to NMOS ring oscillators with 2.5 ns delay/stage and dynamic shift registers with MHz clock rates. These are the first logic circuits fabricated in beam-crystallized silicon on bulk amorphous substrates.

Download Full-text

A Simulation Study of a Gate-All-Around Nanowire Transistor with a Core–Insulator

Micromachines ◽

10.3390/mi11020223 ◽

2020 ◽

Vol 11 (2) ◽

pp. 223 ◽

Cited By ~ 1

Author(s):

Yannan Zhang ◽

Ke Han ◽

and Jiawei Li

Keyword(s):

Metal Oxide ◽

Low Power ◽

Energy Efficient ◽

Field Effect ◽

High Performance ◽

Field Effect Transistors ◽

Future Generation ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Ultra Low Power

Ultra-low power and high-performance logical devices have been the driving force for the continued scaling of complementary metal oxide semiconductor field effect transistors which greatly enable electronic devices such as smart phones to be energy-efficient and portable. In the pursuit of smaller and faster devices, researchers and scientists have worked out a number of ways to further lower the leaking current of MOSFETs (Metal oxide semiconductor field effect transistor). Nanowire structure is now regarded as a promising candidate of future generation of logical devices due to its ultra-low off-state leaking current compares to FinFET. However, the potential of nanowire in terms of off-state current has not been fully discovered. In this article, a novel Core–Insulator Gate-All-Around (CIGAA) nanowire has been proposed, investigated, and simulated comprehensively and systematically based on 3D numerical simulation. Comparisons are carried out between GAA and CIGAA. The new CIGAA structure exhibits low off-state current compares to that of GAA, making it a suitable candidate of future low-power and energy-efficient devices.

Download Full-text