Monolithic 3D Integration of Single-Grain Si TFTs

2008 ◽  
Vol 1066 ◽  
Author(s):  
Mohammad Reza Tajari Mofrad ◽  
Ryoichi Ishihara ◽  
Jaber Derakhshandeh ◽  
Alessandro Baiano ◽  
Johan van der Cingel ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Three Dimensional ◽  
Bottom Layer ◽  
Switching Voltage ◽  
3D Integration ◽  
Monolithically Integrated ◽  
Interconnect Delay ◽  
Single Grain ◽  
Voltage Swing

ABSTRACTVertical stacking of transistors is a promising technology which can realize compact and high-speed integrated circuits (ICs) with a short interconnect delay and increased functionality. Two layers of low-temperature fabricated single-grain thin-film transistors (SG TFTs) have been monolithically integrated. NMOS mobilities are 565 and 393 cm2/Vs and pMOS mobilities are 159 and 141 cm2/Vs, for the top and bottom layers respectively. A three-dimensional (3D) inverter has also been fabricated, with one transistor on the bottom layer and the other on the top layer. The inverters showed an output voltage swing of 0 to 5 V with a switching voltage of around 2 V.

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

2017 ◽  
Vol 139 (2) ◽  
Author(s):  
Leila Choobineh ◽  
Jared Jones ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Resistance ◽  
High Speed ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermal Design ◽  
Electrical Performance ◽  
Physical Parameters ◽  
Interconnect Delay ◽  
3D Ics

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

scholarly journals Evaluation of the Potential Electromagnetic Interference in Vertically Stacked 3D Integrated Circuits

2020 ◽  
Vol 10 (3) ◽  
pp. 748
Author(s):  
Dipesh Kapoor ◽  
Cher Ming Tan ◽  
Vivek Sangwan
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Electromagnetic Interference ◽  
High Speed ◽  
High Performance ◽  
Near Field ◽  
Three Dimensional ◽  
3D Ic ◽  
Three Dimensional Integrated Circuit ◽  
The Impact

Advancements in the functionalities and operating frequencies of integrated circuits (IC) have led to the necessity of measuring their electromagnetic Interference (EMI). Three-dimensional integrated circuit (3D-IC) represents the current advancements for multi-functionalities, high speed, high performance, and low-power IC technology. While the thermal challenges of 3D-IC have been studied extensively, the influence of EMI among the stacked dies has not been investigated. With the decreasing spacing between the stacked dies, this EMI can become more severe. This work demonstrates the potential of EMI within a 3D-IC numerically, and determines the minimum distance between stack dies to reduce the impact of EMI from one another before they are fabricated. The limitations of using near field measurement for the EMI study in stacked dies 3D-IC are also illustrated.

Numerical Simulation of High Speed Single-Grain Cutting Using a Coupled FE-SPH Approach

2013 ◽  
Vol 483 ◽  
pp. 3-8 ◽  
Author(s):  
Rui Dong Shen ◽  
Xiu Mei Wang ◽  
Chun Hui Yang
Keyword(s):  
Numerical Model ◽  
High Speed ◽  
Three Dimensional ◽  
Cutting Speed ◽  
Chip Thickness ◽  
Rake Angle ◽  
High Cutting Speed ◽  
Particle Hydrodynamics ◽  
Single Grain ◽  
Cutting Processes

In this study, to simulate the grinding process for rolled homogeneous armor steel (RHA) 4043, a single-grain cutting process is modeled using a three-dimensional (3-D) numerical model, which is developed using a coupled finite element (FE) - smoothed-particle hydrodynamics (SPH) approach. The proposed numerical model is then employed to investigate the influences of grain negative rake angle (-22°, -31°, and-45°) as well as high and super-high cutting speed ranged from 100 m/s to 260 m/s in the cutting processes. The numerical results show the cutting forces are much lower and the maximum chip thickness is much larger when using a smaller grain negative rake angle.

A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology

2017 ◽  
Vol 26 (11) ◽  
pp. 1750182
Author(s):  
Indrit Myderrizi ◽  
Ali Zeki
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Output Voltage ◽  
High Speed ◽  
Pulse Signal ◽  
Propagation Delay ◽  
Cmos Process ◽  
Down Low ◽  
Voltage Swing ◽  
Output Voltage Swing

With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.

scholarly journals Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Micromachines ◽  
2020 ◽  
Vol 11 (8) ◽  
pp. 741
Author(s):  
Tung-Ying Hsieh ◽  
Ping-Yi Hsieh ◽  
Chih-Chao Yang ◽  
Chang-Hong Shen ◽  
Jia-Min Shieh ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Laser Annealing ◽  
Three Dimensional ◽  
Far Infrared ◽  
Superior Performance ◽  
Nanosecond Laser ◽  
Thermal Budget ◽  
Si Nanowire ◽  
Single Grain ◽  
Low Thermal Budget

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

Three Dimensional Integration with Benzocyclobutene as the Wafer-Bonding Medium

2004 ◽  
Vol 833 ◽  
Author(s):  
Sang Kevin Kim ◽  
Lei Xue ◽  
Sandip Tiwari
Keyword(s):  
Integrated Circuits ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Experimental Results ◽  
Device Layer ◽  
3D Integration ◽  
Wafer Scale ◽  
3D Ics ◽  
Fabrication Procedure ◽  
3D Fabrication

ABSTRACTA successful wafer-scale device layering process for fabricating three-dimensional integrated circuits (3D ICs) using Benzocyclobutene (BCB) is described. In the reported embodiment of the method, a sub-micron thick “donor” device layer is transplanted onto a fully fabricated “host” wafer with BCB as the intervening medium. Experimental results, including RIE study and planarization of BCB processed through the 3D fabrication procedure are reported. We conclude with an approach to alleviate BCB and fabrication induced wafer bowing, which leads to poor wafer to wafer alignment in 3D integration.

Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 118401
Author(s):  
Xiaoxian Liu ◽  
Zhangming Zhu ◽  
Yintang Yang ◽  
Ruixue Ding ◽  
Yuejin Li
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Three Dimensional ◽  
Air Gap ◽  
Through Silicon Vias ◽  
Parasitic Effects ◽  
Silicon Vias

A Review of Recent Advances in Thermal Management in Three Dimensional Chip Stacks in Electronic Systems

2011 ◽  
Vol 133 (4) ◽  
Author(s):  
Vikram Venkatadri ◽  
Bahgat Sammakia ◽  
Krishnaswami Srihari ◽  
Daryl Santos
Keyword(s):  
Thermal Analysis ◽  
Integrated Circuits ◽  
Thermal Management ◽  
Management Strategies ◽  
Research Work ◽  
Experimental Studies ◽  
Three Dimensional ◽  
3D Integration ◽  
The Past ◽  
Planar Circuits

Three dimensional (3D) integration offers numerous electrical advantages like shorter interconnection distances between different dies in the stack, reduced signal delay, reduced interconnect power and design flexibilities. The main enabler of 3D integration is through-silicon-vias (TSVs) and stacking of multiple dies. Irrespective of these advantages, thermal management in 3D stacks poses significant challenges for the implementation of 3D integrated circuits. Even though extensive research work has been done in understanding the thermal management in two dimensional (2D) planar circuits for the past several decades, 3D integration offers a new set of challenges in terms of thermal management, which makes it difficult to readily apply the thermal management strategies available for 2D planar circuits. Over the past decade, some work has been done in thermal analysis and management of 3D stacks but still, knowledge is scattered and a comprehensive understanding is lacking. This research work focuses on bringing together the limited work on thermal analysis and thermal management in 3D vertically integrated circuits available in the literature. A compilation and analysis of the results from investigations on thermal management in 3D stacks is presented in this review with special emphasis on experimental studies conducted on different thermal management strategies. Furthermore, 3D integration technologies, thermal management challenges, and advanced 2D thermal management solutions are discussed.

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