Barrier Properties of Electroless Ni-B UBM for Solder Joining

2015 ◽  
Vol 2015 (1) ◽  
pp. 000862-000867
Author(s):  
Masaru Morita ◽  
Toshiya Akamatsu ◽  
Nobuhiro Imaizumi ◽  
Seiki Sakuyama
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Solid Phase ◽  
Barrier Properties ◽  
Electrode Structure ◽  
Phase Diffusion ◽  
3D Ics ◽  
The Difference ◽  
Electroless Ni ◽  
Plating Layer

As demands accelerate for high density, high speed transmission and low power integrated circuits, 3D-ICs with through-silicon via (TSV) is pursued. In the structure of 3D-ICs, the first die is attached to the second die with micro bump, and the second die is attached to the circuit substrate with a C4 solder bump. The electrode structure of the second die is Cu/Ni UBM. The stress of the Ni-B layer is less than that of the Ni-P layer, and the Ni-B layer can suppress stress and die warpage. The purposes of our study are to clarify the difference in the barrier properties of the Ni-B UBM and Ni-P under bump metal (UBM) and the relevance of the barrier properties of Ni UBM and intermetallic compound (IMC) growth. It was found that an electroless Ni-B plating layer is superior to a Ni-P plating layer for UBM in liquid phase diffusion and in solid phase diffusion, and that a segregated B layer is formed under the IMC layer of a Ni-B land due to reflow soldering. It was estimated that this B layer plays the role of being a barrier layer for solder diffusion.

Applications of Solid Phase Doping in Manufacturing MOS Devices

1990 ◽  
Vol 182 ◽  
Author(s):  
S. F. Gong ◽  
H. T. G. Hentzell ◽  
A. Robertsson
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Field Effect Transistors ◽  
Solid Phase ◽  
Mos Devices ◽  
Transmission Electron ◽  
Heavily Doped ◽  
Si Films ◽  
Secondary Ion ◽  
Si Wafer

AbstractSolid phase doping from Sb heavily-doped Si films has been studied by using transmission electron microscopy and secondary ion mass spectroscopy. Based on the results of the material study, metal-oxidesemiconductor field effect transistors (MOSFETs) made on a (100) Si wafer, and thin film transistors have been implemented. The technique for the MOSFETs suggests the possibility for making small dimensional and high speed integrated circuits by using the method of solid phase doping.

Experimental and Numerical Investigation of Interdie Thermal Resistance in Three-Dimensional Integrated Circuits

2017 ◽  
Vol 139 (2) ◽  
Author(s):  
Leila Choobineh ◽  
Jared Jones ◽  
Ankur Jain
Keyword(s):  
Integrated Circuits ◽  
Thermal Resistance ◽  
High Speed ◽  
Three Dimensional ◽  
Heat Removal ◽  
Thermal Design ◽  
Electrical Performance ◽  
Physical Parameters ◽  
Interconnect Delay ◽  
3D Ics

Three-dimensional integrated circuits (3D ICs) attract much interest due to several advantages over traditional microelectronics design, such as electrical performance improvement and reducing interconnect delay. While the power density of 3D ICs increases because of vertical integration, the available substrate area for heat removal does not change. Thermal modeling of 3D ICs is important for improving thermal and electrical performance. Experimental investigation on the thermal measurement of 3D ICs and determination of key physical parameters in 3D ICs thermal design are curtail. One such important parameter in thermal analysis is the interdie thermal resistance between adjacent die bonded together. This paper describes an experimental method to measure the value of interdie thermal resistance between two adjacent dies in a 3D IC. The effect of heating one die on the temperature of the other die in a two-die stack is measured over a short time period using high-speed data acquisition to negate the effect of boundary conditions. Numerical simulation is performed and based on a comparison between experimental data and the numerical model, the interdie thermal resistance between the two dies is determined. A theoretical model is also developed to estimate the value of the interdie thermal resistance. Results from this paper are expected to assist in thermal design and management of 3D ICs.

Microfabrication research at the National Submicron Facility

1983 ◽  
Vol 41 ◽  
pp. 86-89
Author(s):  
E.D. Wolf
Keyword(s):  
Integrated Circuits ◽  
Particle Physics ◽  
High Speed ◽  
New Technology ◽  
High Energy ◽  
High Energy Particle ◽  
New Science ◽  
Wide Range ◽  
Intermediate Domain ◽  
Circuit Function

Most microelectronics devices and circuits operate faster, consume less power, execute more functions and cost less per circuit function when the feature-sizes internal to the devices and circuits are made smaller. This is part of the stimulus for the Very High-Speed Integrated Circuits (VHSIC) program. There is also a need for smaller, more sensitive sensors in a wide range of disciplines that includes electrochemistry, neurophysiology and ultra-high pressure solid state research. There is often fundamental new science (and sometimes new technology) to be revealed (and used) when a basic parameter such as size is extended to new dimensions, as is evident at the two extremes of smallness and largeness, high energy particle physics and cosmology, respectively. However, there is also a very important intermediate domain of size that spans from the diameter of a small cluster of atoms up to near one micrometer which may also have just as profound effects on society as “big” physics.

Structural changes in silicon-on-insulator material during post-implantation annealing

1986 ◽  
Vol 44 ◽  
pp. 736-737
Author(s):  
C. O. Jung ◽  
S. J. Krause ◽  
S.R. Wilson
Keyword(s):  
Integrated Circuits ◽  
Oxide Layer ◽  
High Speed ◽  
Structural Changes ◽  
Device Fabrication ◽  
Silicon On Insulator ◽  
High Quality ◽  
Radiation Hardened ◽  
Post Implantation ◽  
Very High

Silicon-on-insulator (SOI) structures have excellent potential for future use in radiation hardened and high speed integrated circuits. For device fabrication in SOI material a high quality superficial Si layer above a buried oxide layer is required. Recently, Celler et al. reported that post-implantation annealing of oxygen implanted SOI at very high temperatures would eliminate virtually all defects and precipiates in the superficial Si layer. In this work we are reporting on the effect of three different post implantation annealing cycles on the structure of oxygen implanted SOI samples which were implanted under the same conditions.

TEM study of phosphorus-implanted pseudomorphic Si0.88Ge0.12 on Si(100)

1995 ◽  
Vol 53 ◽  
pp. 468-469
Author(s):  
N. David Theodore ◽  
Donald Y.C Lie ◽  
J. H. Song ◽  
Peter Crozier
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Room Temperature ◽  
Strain Relaxation ◽  
Bipolar Transistors ◽  
Sige Hbt ◽  
Integrated Circuit Manufacturing ◽  
Microstructural Behavior

SiGe is being extensively investigated for use in heterojunction bipolar-transistors (HBT) and high-speed integrated circuits. The material offers adjustable bandgaps, improved carrier mobilities over Si homostructures, and compatibility with Si-based integrated-circuit manufacturing. SiGe HBT performance can be improved by increasing the base-doping or by widening the base link-region by ion implantation. A problem that arises however is that implantation can enhance strain-relaxation of SiGe/Si.Furthermore, once misfit or threading dislocations result, the defects can give rise to recombination-generation in depletion regions of semiconductor devices. It is of relevance therefore to study the damage and anneal behavior of implanted SiGe layers. The present study investigates the microstructural behavior of phosphorus implanted pseudomorphic metastable Si0.88Ge0.12 films on silicon, exposed to various anneals.Metastable pseudomorphic Si0.88Ge0.12 films were grown ~265 nm thick on a silicon wafer by molecular-beam epitaxy. Pieces of this wafer were then implanted at room temperature with 100 keV phosphorus ions to a dose of 1.5×1015 cm-2.

The Radio Probe™: A New Measurement Tool for High Speed Integrated Circuits

2005 ◽  
Author(s):  
Mark Kimball
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Attenuation Factor ◽  
Cost Effective ◽  
Frequency Measurement ◽  
Single Frequency ◽  
Measurement Tool ◽  
Probe Design ◽  
Differential Measurement

Abstract This article presents a novel tool designed to allow circuit node measurements in a radio frequency (RF) integrated circuit. The discussion covers RF circuit problems; provides details on the Radio Probe design, which achieves an input impedance of 50Kohms and an overall attenuation factor of 0 dB; and describes signal to noise issues in the output signal, along with their improvement techniques. This cost-effective solution incorporates features that make it well suited to the task of differential measurement of circuit nodes within an RF IC. The Radio Probe concept offers a number of advantages compared to active probes. It is a single frequency measurement tool, so it complements, rather than replaces, active probes.

Electrical Probing and Surface Imaging of Deep Sub-Micron Integrated Circuits

1999 ◽  
Author(s):  
Kenneth Krieg ◽  
Richard Qi ◽  
Douglas Thomson ◽  
Greg Bridges
Keyword(s):  
High Resolution ◽  
Integrated Circuits ◽  
Real Time ◽  
High Speed ◽  
Time Signal ◽  
Surface Imaging ◽  
Atomic Force ◽  
Submicron Structures ◽  
High Resolution Images ◽  
Capacitive Loading

Abstract A contact probing system for surface imaging and real-time signal measurement of deep sub-micron integrated circuits is discussed. The probe fits on a standard probe-station and utilizes a conductive atomic force microscope tip to rapidly measure the surface topography and acquire real-time highfrequency signals from features as small as 0.18 micron. The micromachined probe structure minimizes parasitic coupling and the probe achieves a bandwidth greater than 3 GHz, with a capacitive loading of less than 120 fF. High-resolution images of submicron structures and waveforms acquired from high-speed devices are presented.

Case study: Prediction and field tests of railway noise and effects of a low-height noise barrier

2020 ◽  
Vol 68 (4) ◽  
pp. 303-314
Author(s):  
Yuna Park ◽  
Hyo-In Koh ◽  
University of Science and Technology, Transpo ◽  
University of Science and Technology, Transpo ◽  
University of Science and Technology, Transpo ◽  
...  
Keyword(s):  
High Speed ◽  
Field Tests ◽  
Residential Areas ◽  
Railway Systems ◽  
Railway Noise ◽  
Sound Levels ◽  
Noise Barrier ◽  
The Difference ◽  
Reduction Effect ◽  
The Impact

Railway noise is calculated to predict the impact of new or reconstructed railway tracks on nearby residential areas. The results are used to prepare adequate counter- measures, and the calculation results are directly related to the cost of the action plans. The calculated values were used to produce noise maps for each area of inter- est. The Schall 03 2012 is one of the most frequently used methods for the production of noise maps. The latest version was released in 2012 and uses various input para- meters associated with the latest rail vehicles and track systems in Germany. This version has not been sufficiently used in South Korea, and there is a lack of standard guidelines and a precise manual for Korean railway systems. Thus, it is not clear what input parameters will match specific local cases. This study investigates the modeling procedure for Korean railway systems and the differences between calcu- lated railway sound levels and measured values obtained using the Schall 03 2012 model. Depending on the location of sound receivers, the difference between the cal- culated and measured values was within approximately 4 dB for various train types. In the case of high-speed trains, the value was approximately 7 dB. A noise-reducing measure was also modeled. The noise reduction effect of a low-height noise barrier system was predicted and evaluated for operating railway sites within the frame- work of a national research project in Korea. The comparison of calculated and measured values showed differences within 2.5 dB.

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