Opening Ratio Effect on Electrowetting Droplet Actuation on Perforated Membranes

2009 ◽  
Author(s):  
Yuejun Zhao ◽  
Sung Kwon Cho
Keyword(s):  
Power Consumption ◽  
Sampling Method ◽  
Critical Issue ◽  
Membrane Area ◽  
Ratio Effect ◽  
Lower Power ◽  
Analytical Results ◽  
Hole Area ◽  
Opening Ratio ◽  
Total Membrane

We have previously developed a microparticle sampling method in which electrowetting-actuated droplets sweep and pick up microparticles trapped on a perforated membrane. In this configuration, a critical issue is to increase the opening ratio (ratio of opening hole area to the total membrane area) in the perforated membrane as much as possible since the higher the opening ratio the lower power consumption in the process of air suction. In contrast, increasing the opening ratio hampers successful electrowetting operations of droplets and thus sampling of microparticles. In this study, we analytically investigate effects of the opening ratio on electrowetting operations. In particular, we are looking at the reversibility of electrowetting operation. Then, we fabricate testing devices to verify the analytical results in the range of the opening ratio up to about 90%. We will also discuss detailed challenging issues in microfabrication to reach such a high opening ratio.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

A LOW-POWER AND HIGH-SPEED D FLIP-FLOP USING A SINGLE LATCH

2002 ◽  
Vol 11 (01) ◽  
pp. 51-55
Author(s):  
ROBERT C. CHANG ◽  
L.-C. HSU ◽  
M.-C. SUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Operating Frequency ◽  
Flip Flop ◽  
Lower Power ◽  
Simulation Results ◽  
Hspice Simulation

A novel low-power and high-speed D flip-flop is presented in this letter. The flip-flop consists of a single low-power latch, which is controlled by a positive narrow pulse. Hence, fewer transistors are used and lower power consumption is achieved. HSPICE simulation results show that power dissipation of the proposed D flip-flop has been reduced up to 76%. The operating frequency of the flip-flop is also greatly increased.

scholarly journals Single-Electron Memories

VLSI Design ◽  
1998 ◽  
Vol 8 (1-4) ◽  
pp. 219-223 ◽  
Author(s):  
Christoph Wasshuber ◽  
Hans Kosina ◽  
Siegfried Selberherr
Keyword(s):  
Power Consumption ◽  
Room Temperature ◽  
State Of The Art ◽  
Memory Cell ◽  
Single Electron ◽  
Lower Power ◽  
Memory Chip ◽  
Single Electronics ◽  
Background Charge ◽  
Random Background

One of the most promising applications of single-electronics is a single-electron memory chip. Such a chip would have orders of magnitude lower power consumption compared to state-of-the-art dynamic memories, and would allow integration densities beyond the tera bit chip.We studied various single-electron memory designs. Additionally we are proposing a new memory cell which we call the T-memory cell. This cell can be manufactured with state-of-the-art lithography, it operates at room temperature and shows a strong resistance against random background charge.

High-Performance Reconfigurable Computing

2019 ◽  
pp. 731-744
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-performance reconfigurable computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to general-purpose processors. Better performance and lower power consumption could be achieved using application-specific integrated circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter, the authors provide a description of reconfigurable hardware for high-performance computing.

High-Performance Reconfigurable Computing

2018 ◽  
pp. 4018-4029
Author(s):  
Mário Pereira Vestias
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Reconfigurable Computing ◽  
High Performance ◽  
General Purpose ◽  
Reconfigurable Hardware ◽  
Coarse Grained ◽  
Lower Power ◽  
Fine Grained ◽  
Application Specific

High-Performance Reconfigurable Computing systems integrate reconfigurable technology in the computing architecture to improve performance. Besides performance, reconfigurable hardware devices also achieve lower power consumption compared to General-Purpose Processors. Better performance and lower power consumption could be achieved using Application Specific Integrated Circuit (ASIC) technology. However, ASICs are not reconfigurable, turning them application specific. Reconfigurable logic becomes a major advantage when hardware flexibility permits to speed up whatever the application with the same hardware module. The first and most common devices utilized for reconfigurable computing are fine-grained FPGAs with a large hardware flexibility. To reduce the performance and area overhead associated with the reconfigurability, coarse-grained reconfigurable solutions has been proposed as a way to achieve better performance and lower power consumption. In this chapter we will provide a description of reconfigurable hardware for high performance computing.

Challenges in 3D Inspection of Micro Bumps Used in 3D Packaging

2012 ◽  
Vol 2012 (1) ◽  
pp. 000542-000547 ◽  
Author(s):  
Reza Asgari
Keyword(s):  
Power Consumption ◽  
Wafer Bonding ◽  
Field Programmable Gate Array ◽  
Laser Triangulation ◽  
3D Measurement ◽  
Lower Power ◽  
Small Pitch ◽  
Field Programmable ◽  
3D Packaging ◽  
2D And 3D

2.5D/3D devices are the next major packaging technologies, driven by the need for more functionality, lower power consumption and smaller footprint. Many device manufacturers are devoting capital to develop their own processes and some are already shipping devices such as FPGA (Field Programmable Gate Array) on interposers. 3D packages often require hundreds of thousands of I/O per die. Micro Pillar bumps and C4 bumps are the main bump geometries used in 3D packages as their small pitch and size allow the required number of I/Os. Inspecting these bumps throughout the process is critical because failure after chip to chip or chip to wafer bonding is very costly. This paper describes the use of a camera and laser triangulation to provide complete 2D and 3D measurement and inspection capability.

On the Diminished-1 Modulo 2n+1 Addition and Subtraction

2019 ◽  
Vol 29 (05) ◽  
pp. 2030005
Author(s):  
Constantinos Efstathiou ◽  
Kiamal Pekmestzi ◽  
Nikolaos Moshopoulos
Keyword(s):  
Power Consumption ◽  
Lower Power ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Addition And Subtraction ◽  
Arithmetic Units ◽  
Prefix Adders

In this work, the design of the diminished-1 modulo [Formula: see text] adders, subtractors and adders/subtractors are examined. Some of the existing modulo [Formula: see text] adders, subtractors and adder/subtractors are redesigned and improved. Compared to other existing implementations, the proposed subtractor and adder/subtractors offer reduced area complexity and lower power consumption, while operating at the same speed. All the considered architectures are modified parallel-prefix adders with fast input carry processing. The totally parallel-prefix and carry look ahead implementation of the proposed arithmetic units are also discussed.

Analysis and comparison of fast multiplier circuits based on different parameters

2018 ◽  
Vol 7 (3) ◽  
pp. 1189
Author(s):  
Mr Aaron D’costa ◽  
Dr Abdul Razak ◽  
Dr Shazia Hasan
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Electronic Circuit ◽  
Vlsi Circuit ◽  
Silicon Area ◽  
Lower Power ◽  
Digital Electronics ◽  
Design Specifications ◽  
Important Design ◽  
Multiplier Circuit

Digital multiplier circuits are used in computers. A multiplier is an electronic circuit used in digital electronics to multiply two binary numbers. Multiplier circuits are used in ALU for binary multiplication of signed and unsigned numbers. The delay, area and power consumption are the 3 most important design specifications a chip designer has to consider. Delay of the circuit is directly proportional to the delay of a multiplier. Increased delay in the multiplier leads to higher delay in the circuit. Therefore research is carried out as to how to reduce the delay of the multiplier block so as to reduce the delay of whole circuit. The main purpose is to deal with high speed and lower power consumption even after decreasing the silicon area. This makes them well-suited for numerous complex and convenient VLSI circuit implementations. The fact however, remains that area and speed are two contradictory performance restrictions. Hence, increase in speed always results in the use of more and complex hardware. Different arithmetic techniques can be used to implement different multiplier circuits. The focus of this paper is to implement various multiplier circuit and compare them. The timing signals can be observed using software such as Modelsim and Xilinx.  

Gas separation process: analysis of composite membranes based on alumina/PVDF at lower power consumption energy

2012 ◽  
Vol 51 (1-3) ◽  
pp. 606-608 ◽  
Author(s):  
Dionísio da Silva Biron ◽  
Camila Cherubini ◽  
Venina dos Santos ◽  
Lucas Gomes ◽  
Andréa Schneider ◽  
...  
Keyword(s):  
Power Consumption ◽  
Gas Separation ◽  
Process Analysis ◽  
Composite Membranes ◽  
Separation Process ◽  
Lower Power ◽  
Consumption Energy

scholarly journals A quantitative model of traffic between plasma membrane and secondary lysosomes: evaluation of inflow, lateral diffusion, and degradation.

1988 ◽  
Vol 107 (6) ◽  
pp. 2109-2115 ◽  
Author(s):  
J P Draye ◽  
P J Courtoy ◽  
J Quintart ◽  
P Baudhuin
Keyword(s):  
Plasma Membrane ◽  
Half Life ◽  
Plasma Membranes ◽  
Lateral Diffusion ◽  
Quantitative Model ◽  
Lysosomal Membrane ◽  
Membrane Area ◽  
Rat Fibroblasts ◽  
Secondary Lysosomes ◽  
Total Membrane

We present here a mathematical model that accounts for the various proportions of plasma membrane constituents occurring in the lysosomal membrane of rat fibroblasts (Draye, J.-P., J. Quintart, P. J. Courtoy, and P. Baudhuin. 1987. Eur. J. Biochem. 170: 395-403; Draye, J.-P., P. J. Courtoy, J. Quintart, and P. Baudhuin. 1987. Eur. J. Biochem. 170:405-411). It is based on contents of plasma membrane markers in purified lysosomal preparations, evaluations of their half-life in lysosomes and measurements of areas of lysosomal and plasma membranes by morphometry. In rat fibroblasts, structures labeled by a 2-h uptake of horseradish peroxidase followed by a 16-h chase (i.e., lysosomes) occupy 3% of the cellular volume and their total membrane area corresponds to 30% of the pericellular membrane area. Based on the latter values, the model predicts the rate of inflow and outflow of plasma membrane constituents into lysosomal membrane, provided their rate of degradation is known. Of the bulk of polypeptides iodinated at the cell surface, only 4% reach the lysosomes every hour, where the major part (integral of 83%) is degraded with a half-life in lysosomes of integral to 0.8 h. For specific plasma membrane constituents, this model can further account for differences in the association to the lysosomal membrane by variations in the rate either of lysosomal degradation, of inflow along the pathway from the pericellular membrane to the lysosomes, or of lateral diffusion.

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