scholarly journals Design and Implementation of Ternary Logic Integrated Circuits by Using Novel Two-Dimensional Materials

2019 ◽  
Vol 9 (20) ◽  
pp. 4212 ◽  
Author(s):  
Mingqiang Huang ◽  
Xingli Wang ◽  
Guangchao Zhao ◽  
Philippe Coquet ◽  
Bengkang Tay
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
2D Materials ◽  
Two Dimensional ◽  
Ternary Logic ◽  
Chip Area ◽  
Logic Devices ◽  
Ripple Carry Adder ◽  
Data Density

With the approaching end of Moore’s Law (that the number of transistors in a dense integrated circuit doubles every two years), the logic data density in modern binary digital integrated circuits can hardly be further improved due to the physical limitation. In this aspect, ternary logic (0, 1, 2) is a promising substitute to binary (0, 1) because of its higher number of logic states. In this work, we carry out a systematical study on the emerging two-dimensional (2D) materials (MoS2 and Black Phosphorus)-based ternary logic from individual ternary logic devices to large scale ternary integrated circuits. Various ternary logic devices, including the standard ternary inverter (STI), negative ternary inverter (NTI), positive ternary inverter (PTI) and especially the ternary decrement cycling inverter (DCI), have been successfully implemented using the 2D materials. Then, by taking advantage of the optimized ternary adder algorithm and the novel ternary cycling inverter, we design a novel ternary ripple-carry adder with great circuitry simplicity. Our design shows about a 50% reduction in the required number of transistors compared to the existing ternary technology. This work paves a new way for the ternary integrated circuits design, and shows potential to fulfill higher logic data density and a smaller chip area in the future.

scholarly journals An Artificial Neutral Network Chip Based on Two-Dimensional Semiconductor

2020 ◽  
Author(s):  
Shunli Ma ◽  
Tianxiang Wu ◽  
Xinyu Chen ◽  
Yin Wang ◽  
Hongwei Tang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
Field Effect Transistors ◽  
Recognition Rate ◽  
Activation Function ◽  
Machine Learning Algorithms ◽  
Two Dimensional ◽  
Wafer Scale ◽  
Large Current

Abstract Two-dimensional semiconductors can be used to build integrated circuits for running artificial neural networks (ANN) with higher energy efficiency. The implementation of an ANN with 2D semiconductors has been held back by the large-scale and high-quality transistors required for running machine learning algorithms. Here we demonstrate the first functional MoS2 analog ANN integrated circuit, including memory, multiply-and-accumulate (MAC), activation function, and weight update circuits. The ANN integrated circuit is realized through 818 field effect transistors (FETs) with wafer-scale and high-homogeneity MoS2 film. The large current on/off ratio and output linearity of these MoS2 FETs allow the realization of convolutional and activation function circuits with a few number of transistors. This ANN can be used for recognizing tactile digit, showing the recognition rate exceeding 97%. Our work demonstrates wafer-scale processing of a 2D semiconductor for building integrated circuits with the functions of AI computation.

Ultrasensitive broadband photodetectors based on two-dimensional Bi2O2Te films

2021 ◽  
Author(s):  
Pin Tian ◽  
Hongbo Wu ◽  
Libin Tang ◽  
Jinzhong Xiang ◽  
Rongbin Ji ◽  
...  
Keyword(s):  
Large Scale ◽  
2D Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Photocurrent Density ◽  
Short Wave ◽  
Oxide Semiconductor ◽  
Light Illumination ◽  
Two Dimensional ◽  
Weak Light

Abstract Two-dimensional (2D) materials exhibit many unique optical and electronic properties that are highly desirable for application in optoelectronics. Here, we report the study of photodetector based on 2D Bi2O2Te grown on n-Si substrate. The 2D Bi2O2Te material was transformed from sputtered Bi2Te3 ultrathin film after rapid annealing at 400 ℃ for 10 min in air atmosphere. The photodetector was capable of detecting a broad wavelength from 210 nm to 2.4 μm with excellent responsivity of up to 3x105 and 2x104 AW-1, and detectivity of 4x1015 and 2x1014 Jones at deep ultraviolet (UV) and short-wave infrared (SWIR) under weak light illumination, respectively. The effectiveness of 2D materials in weak light detection was investigated by analysis of the photocurrent density contribution. Importantly, the facile growth process with low annealing temperature would allow direct large-scale integration of the 2D Bi2O2Te materials with complementary metal-oxide–semiconductor (CMOS) technology.

RF Modules (Tx–Rx) with Multifunctional MMICs

2017 ◽  
Vol 2017 (NOR) ◽  
pp. 1-5
Author(s):  
Martin Oppermann ◽  
Ralf Rieger
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Next Generation ◽  
Electronic Warfare ◽  
Chip Area ◽  
Operating Modes ◽  
Half Wavelength ◽  
X Band ◽  
Physical Channel ◽  
Promising Solution

Abstract Next generation RF sensor modules for multifunction active electronically steered antenna (AESA) systems will need a combination of different operating modes, such as radar, electronic warfare (EW) functionalities and communications/datalinks within the same antenna frontend. They typically operate in C-Band, X-Band and Ku-Band and imply a bandwidth requirement of more than 10 GHz. For the realisation of modern active electronically steered antennas, the transmit/receive (T/R) modules have to match strict geometry demands. A major challenge for these future multifunction RF sensor modules is dictated by the half-wavelength antenna grid spacing, that limits the physical channel width to < 12 mm or even less, depending on the highest frequency of operation with accordant beam pointing requirements. A promising solution to overcome these geometry demands is the reduction of the total monolithic microwave integrated circuit (MMIC) chip area, achieved by integrating individual RF functionalities, which are commonly achieved through individual integrated circuits (ICs), into new multifunctional (MFC) MMICs. Various concepts, some of them already implemented, towards next generation RF sensor modules will be discussed and explained in this work.

scholarly journals Organic printed photonics: From microring lasers to integrated circuits

2015 ◽  
Vol 1 (8) ◽  
pp. e1500257 ◽  
Author(s):  
Chuang Zhang ◽  
Chang-Ling Zou ◽  
Yan Zhao ◽  
Chun-Hua Dong ◽  
Cong Wei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flexible Electronics ◽  
Integrated Circuit ◽  
Large Scale ◽  
Rapid Development ◽  
Light Signal ◽  
Photonic Integrated Circuit ◽  
Printing Technique ◽  
On Chip ◽  
Silicon Based

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

A Comprehensive Test Compression Scheme Based on Precomputed Test Sets

2013 ◽  
Vol 756-759 ◽  
pp. 533-541
Author(s):  
Zhi Jian Tian ◽  
Fa Yong Zhao
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Large Scale ◽  
Test Pattern ◽  
Compression Scheme ◽  
Run Length ◽  
Rearrangement Algorithm ◽  
Long Run ◽  
Assignment Strategy ◽  
Run Lengths

To cope with increasingly rigorous challenges that large scale digital integrated circuit testing is confronted with, a comprehensive compression scheme consisting of test-bit rearrangement algorithm, run-length assignment strategy and symmetrical code is proposed. The presented test-bit rearrangement algorithm can fasten dont-care bits, 0s or 1s in every test pattern on one of its end to the greatest extent so as to lengthen end-run blocks and decrease number of short run-lengths. A dynamical dont-care assignment strategy based on run-lengths can be used to specify the remaining dont-care bits after the test-bit rearrangement, which can decrease run-length splitting and maximize length of run-lengths. The symmetrical code benefits from long run-lengths and only uses 2 4-bit short code words to identify end-run blocks almost as long as a test pattern, and hence the utilization ratio of code words can be heightened. The presented experiment results show that the proposed comprehensive scheme can obtain very higher data compression ratios than other compression ones published up to now, especially for large scale digital integrated circuits, and considerably decrease test power dissipations.

scholarly journals Free Space Intra-Datacenter Interconnects Based on 2D Optical Beam Steering Enabled by Photonic Integrated Circuits

Photonics ◽  
2018 ◽  
Vol 5 (3) ◽  
pp. 21 ◽  
Author(s):  
Charidimos Chaintoutis ◽  
Behnam Shariati ◽  
Adonis Bogris ◽  
Paul Dijk ◽  
Chris Roeloffzen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Data Center ◽  
Free Space ◽  
Large Scale ◽  
Beam Steering ◽  
Optical Beam ◽  
Switching Network ◽  
Free Space Optical ◽  
Data Center Networks

Data centers are continuously growing in scale and can contain more than one million servers spreading across thousands of racks; requiring a large-scale switching network to provide broadband and reconfigurable interconnections of low latency. Traditional data center network architectures, through the use of electrical packet switches in a multi-tier topology, has fundamental weaknesses such as oversubscription and cabling complexity. Wireless intra-data center interconnection solutions have been proposed to deal with the cabling problem and can simultaneously address the over-provisioning problem by offering efficient topology re-configurability. In this work we introduce a novel free space optical interconnect solution for intra-data center networks that utilizes 2D optical beam steering for the transmitter, and high bandwidth wide-area photodiode arrays for the receiver. This new breed of free space optical interconnects can be developed on a photonic integrated circuit; offering ns switching at sub-μW consumption. The proposed interconnects together with a networking architecture that is suitable for utilizing those devices could support next generation intra-data center networks, fulfilling the requirements of seamless operation, high connectivity, and agility in terms of the reconfiguration time.

scholarly journals Large-area integration of two-dimensional materials and their heterostructures by wafer bonding

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Arne Quellmalz ◽  
Xiaojing Wang ◽  
Simon Sawallich ◽  
Burkay Uzlu ◽  
Martin Otto ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Semiconductor Manufacturing ◽  
Large Scale ◽  
Hexagonal Boron Nitride ◽  
2D Materials ◽  
High Volume ◽  
Two Dimensional ◽  
Wafer Level ◽  
Large Area ◽  
Wide Range

AbstractIntegrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to $$4520\;{\mathrm{cm}}^2{\mathrm{V}}^{ - 1}{\mathrm{s}}^{ - 1}$$ 4520 cm 2 V − 1 s − 1 . Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing.

The Challenge of GaAs Heterojunction Bipolar Transistor Integrated Circuit Technology.

1988 ◽  
Vol 144 ◽  
Author(s):  
Han-Tzong Yuan
Keyword(s):  
Integrated Circuits ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
Large Scale ◽  
Ohmic Contacts ◽  
Bipolar Transistors ◽  
Bipolar Transistor ◽  
Heterojunction Bipolar Transistor ◽  
The Status ◽  
Impurity Doping

ABSTRACTThe status and progress of AlGaAs/GaAs heterojunction bipolar transistor integrated circuits are reviewed. The challenge of fabricating large-scale integrated circuits using heterojunction bipolar transistors is discussed. Specifically, the issues related to low defect epitaxial materials, localized impurity doping techniques, simple and reliable ohmic contacts, and multilevel interconnects are examined.

Preparation of Hexaphenylamine Cyclotriphosphazene and its Green Flame Retardance on Epoxy Molding Compound for Large-Scale Integrated Circuit Packaging

2011 ◽  
Vol 239-242 ◽  
pp. 1386-1390
Author(s):  
Ming Shan Yang ◽  
Lin Kai Li
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Flame Retardants ◽  
Large Scale ◽  
Reaction Rate ◽  
Flame Retardance ◽  
Epoxy Molding Compound ◽  
Molding Compound ◽  
Synthesis Parameters ◽  
Halogen Free

The hexaphenylamine cyclotriphosphazene (HPACTPZ) was synthesized using titrating technology of hexachlorocyclotriphosphazene solution and the synthesis parameters were investigated, and the structure of HPACTPZ was analyzed by FTIR and NMR in this paper. Using HPACTPZ synthesized in the work as flame retardant, the epoxy molding compound(EMC) for packaging of large-scale integrated circuits with halogen-free flame retardance was prepared. The results have shown that the flame retardance of EMC flame-retardanced by HPACTPZ was up to UL 94 V0 rating(3.2mm) and the oxygen index of the EMC was up to 35.8%, which indicates that HPACTPZ has much better flame retardance for EMC than traditional halogen flame-retardants. Meanwhile, HPACTPZ accelerated the curing reaction rate of EMC, which can be used for manufacturing the quick-curing EMCs or afterward-curing-free EMCs.

Gallium arsenide electronics in the marketplace

1992 ◽  
Vol 70 (10-11) ◽  
pp. 943-945
Author(s):  
Paul R. Jay.
Keyword(s):  
Gallium Arsenide ◽  
Integrated Circuits ◽  
Integrated Circuit ◽  
High Speed ◽  
Large Scale ◽  
Low Cost ◽  
Logic Gates ◽  
Process Technology ◽  
Maximum Benefit ◽  
Technological Developments

The last few years have seen a significant emergence of real product applications using gallium arsenide metal semi-conductor field effect transistor technology. These applications range from large volume consumer markets based on small low-cost GaAs integrated circuits to high-end supercomputer products using very large scale integrated GaAs chips containing up to 50 000 logic gates. This situation represents substantial advances in many areas: materials technology, device and integrated circuit process technology, packaging and high speed testing, as well as appropriate system design to obtain maximum benefit from the GaAs technology. This paper reviews some recent commercial successes, and considers commonalities existing between them in the context of recent technological developments.

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