Lateral transistor structure optimization with respect to current gain

1987 ◽  
Vol 65 (8) ◽  
pp. 991-994
Author(s):  
Ljubisa Ristic ◽  
Henry P. Baltes ◽  
Igor Filanovsky ◽  
David R. Briglio ◽  
Tom Smy ◽  
...  
Keyword(s):  
Electric Field ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Current Gain ◽  
Bottom Surface ◽  
Transistor Structure ◽  
Lateral Electric Field ◽  
Neutral Base ◽  
Additional Processing ◽  
Order Of Magnitude

An investigation of a novel lateral transistor structure fabricated in standard 4 μm complementary metal oxide semiconductor technology without any additional processing steps is presented. Inherent in the structure is the potential of modulating the lateral electric field in the neutral base region. An additional characteristic of this structure is the reduced bottom surface of the emitter, which diminishes the parasitic action of vertically injected carriers. The results show that because of the lateral electric field, the common-emitter static current gain at high currents can be increased by at least an order of magnitude.

scholarly journals Voltage control of unidirectional anisotropy in ferromagnet-multiferroic system

2018 ◽  
Vol 4 (11) ◽  
pp. eaat4229 ◽  
Author(s):  
Sasikanth Manipatruni ◽  
Dmitri E. Nikonov ◽  
Chia-Ching Lin ◽  
Bhagwati Prasad ◽  
Yen-Lin Huang ◽  
...  
Keyword(s):  
Electric Field ◽  
Exchange Bias ◽  
Room Temperature ◽  
Uniaxial Anisotropy ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
State Variables ◽  
Ultralow Energy ◽  
Unidirectional Anisotropy ◽  
Beyond Cmos

Demonstration of ultralow energy switching mechanisms is imperative for continued improvements in computing devices. Ferroelectric (FE) and multiferroic (MF) order and their manipulation promise an ideal combination of state variables to reach attojoule range for logic and memory (i.e., ~30× lower switching energy than nanoelectronics). In BiFeO3(BFO), the coupling between the antiferromagnetic (AFM) and FE order is robust at room temperature, scalable in voltage, stabilized by the FE order, and can be integrated into a fabrication process for a beyond-CMOS (complementary metal-oxide semiconductor) era. The presence of the AFM order and a canted magnetic moment in this system causes exchange interaction with a ferromagnet such as Co0.9Fe0.1or La0.7Sr0.3MnO3. Previous research has shown that exchange coupling (uniaxial anisotropy) can be controlled with an electric field. However, voltage modulation of unidirectional anisotropy, which is preferred for logic and memory technologies, has not yet been demonstrated. Here, we present evidence for electric field control of exchange bias of laterally scaled spin valves that is exchange coupled to BFO at room temperature. We show that the exchange bias in this bilayer is robust, electrically controlled, and reversible. We anticipate that magnetoelectricity at these scaled dimensions provides a powerful pathway for computing beyond modern nanoelectronics by enabling a new class of nonvolatile, ultralow energy computing elements.

scholarly journals Array of Resonant Electromechanical Nanosystems: A Technological Breakthrough for Uncooled Infrared Imaging

Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 401 ◽  
Author(s):  
Laurent Duraffourg ◽  
Ludovic Laurent ◽  
Jean-Sébastien Moulet ◽  
Julien Arcamone ◽  
Jean-Jacques Yon
Keyword(s):  
Infrared Imaging ◽  
Thermal Response ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Integration Time ◽  
Ir Radiation ◽  
Torsional Mode ◽  
Order Of Magnitude ◽  
Frequency Changes ◽  
Uncooled Infrared Imaging

Microbolometers arethe most common uncooled infrared techniques that allow 50 mK-temperature resolution to be achieved on-scene. However, this approach struggles with both self-heating, which is inherent to the resistive readout principle, and 1/f noise. We present an alternative approach that consists of using micro/nanoresonators vibrating according to a torsional mode, and whose resonant frequency changes with the incident IR-radiation. Dense arrays of such electromechanical structures were fabricated with a 12 µm pitch at low temperature, allowing their integration on complementary metal-oxide-semiconductor (CMOS) circuits according to a post-processing method. H-shape pixels with 9 µm-long nanorods and a cross-section of 250 nm × 30 nm were fabricated to provide large thermal responses, whose experimental measurements reached up to 1024 Hz/nW. These electromechanical resonators featured a noise equivalent power of 140 pW for a response time of less than 1 ms. To our knowledge, these performances are unrivaled with such small dimensions. We also showed that a temperature sensitivity of 20 mK within a 100 ms integration time is conceivable at a 12 µm pitch by co-integrating the resonators with their readout electronics, and suggesting a new readout scheme. This sensitivity could be reached short-term by depositing on top of the nanorods a vanadium oxide layer that had a phase-transition that could possibly enhance the thermal response by one order of magnitude.

scholarly journals The Development of CMOS Amperometric Sensing Chip with a Novel 3-Dimensional TiN Nano-Electrode Array

Sensors ◽  
2019 ◽  
Vol 19 (5) ◽  
pp. 994 ◽  
Author(s):  
Chun-Lung Lien ◽  
Chiun-Jye Yuan
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Electrode Array ◽  
High Sensitivity ◽  
Complementary Metal Oxide Semiconductor ◽  
Electrochemical Sensing ◽  
Oxide Semiconductor ◽  
High Catalytic Activity ◽  
Detection Range ◽  
3 Dimensional

An electrochemical sensing chip with an 8 × 8 array of titanium nitride three-dimensional nano-electrodes (TiN 3D-NEA) was designed and fabricated via a standard integrated complementary metal oxide semiconductor process. Each nano-electrode in 3D-NEA exhibited a pole-like structure with a radius of 100 nm and a height of 35 nm. The numeric simulation showed that the nano-electrode with a radius of around 100 nm exhibited a more uniformly distributed electric field and a much higher electric field magnitude compared to that of the microelectrode. Cyclic voltammetry study with Ru(NH3)63+ also revealed that the TiN 3D-NEA exhibited a much higher current density than that obtained from the microelectrode by two orders of magnitude. Further studies showed that the electrocatalytical reduction of hydrogen peroxide (H2O2) could occur on a TiN 3D-NEA-based sensing chip with a high sensitivity of 667.2 mA⋅mM−1⋅cm−2. The linear detection range for H2O2 was between 0.1 μM and 5 mM with a lowest detection limit of 0.1 μM. These results indicated that the fabricated TiN 3D-NEA exhibited high catalytic activity and sensitivity to H2O2 and could be a promising sensor for H2O2 measurement.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

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