NUMERICAL INVESTIGATION ON THE TEMPERATURE DEPENDENCE OF THE CYLINDRICAL-GATE-ALL-AROUND Si-NW-FET

2011 ◽  
Vol 25 (29) ◽  
pp. 2269-2278 ◽  
Author(s):  
SEYED ALI SEDIGH-ZYIABARI ◽  
KAMYAR SAGHAFI ◽  
RAHIM FAEZ ◽  
MOHAMMAD KAZEM MORAVVEJ-FARSHI
Keyword(s):  
Temperature Dependence ◽  
Numerical Investigation ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Energy Band Structure ◽  
Linear Functions ◽  
Effect Of Temperature ◽  
Si Nanowire ◽  
Effect Transistor

We report the results of our numerical investigation on the temperature dependence of the characteristics of the cylindrical gate-all-around Si nanowire field effect transistor ( Si -NW-FET). Assuming the effect of temperature on the energy band structure of Si just like the effect of strain, we simulate the transistor characteristics at various temperatures (50 K ≤ T ≤ 300 K ). In this investigation, we demonstrate the temperature dependence of the transistor sub-threshold swing and the threshold voltage are both linear functions of the temperature, represented by 61.5 × (T/300) + 63.4 (mV/decade) and 220–140 × (T/300-1) (mV). By calculating the IDS - T characteristics for VDS = 0.4 V and various VGS, we show that the temperature sensitivity of the drain current defined as the slope of the IDS - T plot, for a given VGS, is independent of the temperature and increases with VGS in a quadratic manner [- 150 × (VGS - 0.50)2 + 8.5 (nA/K)]. Ultimately, the dependence of the transistor delay time on temperature will be presented.

Temperature Dependence of Low Frequency Noise in Silicon on Insulator Tunneling Field Effect Transistor

2020 ◽  
Vol 20 (8) ◽  
pp. 4699-4703
Author(s):  
Hyun-Dong Song ◽  
Hyeong-Sub Song ◽  
Sunil Babu Eadi ◽  
Hyun-Woong Choi ◽  
Ga-Won Lee ◽  
...  
Keyword(s):  
Temperature Dependence ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Low Frequency ◽  
Drain Current ◽  
Silicon On Insulator ◽  
Frequency Noise ◽  
Increase With Increase ◽  
Effect Transistor ◽  
Insulator Substrate

In this work, noise mechanism of a tunneling field-effect transistor (TFET) on a silicon-on-insulator substrate was studied as a function of temperature. The results show that the drain current and subthreshold slope increase with increase in temperature. This temperature dependence is likely caused by the generation of greater current flow owing to decreased silicon band gap and leakage. Further, the TFET noise decreases with increase in temperature. Therefore, the effective tunneling length between the source and the channel appears to decrease and Poole–Frenkel tunneling occurs.

scholarly journals Electrical characterization of si nanowire GAA-TFET based on dimensions downscaling

2021 ◽  
Vol 11 (1) ◽  
pp. 780
Author(s):  
Firas Natheer Abdul-Kadir ◽  
Yasir Hashim ◽  
Muhammad Nazmus Shakib ◽  
Faris Hassan Taha
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Drain Current ◽  
Oxide Thickness ◽  
Si Nanowire ◽  
Effect Transistor ◽  
Current Characteristics

This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.

Temperature Sensitivity Analysis of Extended Source Double Gate Tunnel Field Effect Transistor

2021 ◽  
Author(s):  
Dharmender Nishad ◽  
Kaushal Nigam ◽  
Satyendra Kumar
Keyword(s):  
Temperature Sensitivity ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Effect Of Temperature ◽  
Double Gate ◽  
Extended Source ◽  
Temperature Variations ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract Temperature-induced performance variation is one of the main concerns of the conventional stack gate oxide double gate tunnel field-effect transistor (SGO-DG-TFET). In this regard, we investigate the temperature sensitivity of extended source double gate tunnel field-effect transistor (ESDG-TFET). For this, we have analyzed the effect of temperature variations on the transfer characteristics, analog/RF, linearity and distortion figure of merits (FOMs) using technology computer aided design (TCAD) simulations. Further, the temperature sensitivity performance is compared with conventional SGO-DG-TFET. The comparative analysis shows that ESDG-TFET is less sensitive to temperature variations compared to the conventional SGO-DG-TFET. Therefore, this indicates that ESDG-TFET is more reliable for low-power, high-frequency applications at a higher temperature compared to conventional SGO-DG-TFET.

scholarly journals An Improved UU-MESFET with High Power Added Efficiency

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 573 ◽  
Author(s):  
Hujun Jia ◽  
Mei Hu ◽  
Shunwei Zhu
Keyword(s):  
Breakdown Voltage ◽  
Threshold Voltage ◽  
High Power ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Power Added Efficiency ◽  
Effect Transistor ◽  
The Relationship

An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

5A 1300V Trenched and Implanted 4H-SiC Vertical JFET

2012 ◽  
Vol 229-231 ◽  
pp. 824-827 ◽  
Author(s):  
Gang Chen ◽  
Xiao Feng Song ◽  
Song Bai ◽  
Li Li ◽  
Yun Li ◽  
...  
Keyword(s):  
Ohmic Contact ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Vertical Channel ◽  
Drain Current ◽  
Gate Bias ◽  
Blocking Voltage ◽  
Drain Bias ◽  
Effect Transistor ◽  
Lift Off

A silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) was fabricated based on in-house SiC epitaxial wafer with lift-off trenched and implanted method. Its blocking voltage exceeds 1300V at gate bias VG = -6V and forward drain current is in excess of 5A at gate bias VG = 3V and drain bias VD = 3V. The SiC VJFET device’s current density is 240A/cm2 at VG= 3V and VD = 3V, with related specific on-resistance 8.9mΩ•cm2. Further analysis reveals that the on-resistance depends greatly on ohmic contact resistance and the bonding spun gold. The specific on-resistance can be further reduced by improving the doping concentration of SiC channel epilayer and the device’s ohmic contact.

Partial Dissolution of Charge Order Phase Observed in -(BEDT-TTF)2PF6 Single Crystal Field Effect Transistor

2016 ◽  
Vol 16 (4) ◽  
pp. 3267-3272
Author(s):  
Masatoshi Sakai ◽  
Norifumi Moritoshi ◽  
Shigekazu Kuniyoshi ◽  
Hiroshi Yamauchi ◽  
Kazuhiro Kudo ◽  
...  
Keyword(s):  
Electric Field ◽  
Single Crystal ◽  
Temperature Dependence ◽  
Crystal Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Conductance ◽  
Charge Order ◽  
Crystal Field Effect ◽  
Effect Transistor

The effect of an applied gate electric field on the charge-order phase in β-(BEDT-TTF)2PF6 single-crystal field-effect transistor structure was observed at around room temperature by technical improvement with respect to sample preparation and electrical measurements. A relatively slight but systematic increase of the electrical conductance induced by the applied gate electric field and its temperature dependence was observed at around the metal-insulator transition temperature (TMI). The temperature dependence of the modulated electrical conductance demonstrated that TMI was shifted toward the lower side by application of a gate electric field, which corresponds to partial dissolution of the charge-order phase. The thickness of the partially dissolved charge order region was estimated to be several score times larger than the charge accumulation region.

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